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Part: DAC1231LCN
Category:
Data Conversion
-> Multiplying Data Converters
Description: 12-bit, P Compatible, Double-buffered D to a Converters
Company: National Semiconductor Corporation
Datasheet: Download DAC1231LCN datasheet File size : 846 kB
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MICRO-DAC DAC1208 DAC1209 DAC1210 DAC1230 DAC1231 DAC1232 12-Bit mP Compatible Double-Buffered D to A Converters
February 1995
MICRO-DAC TM DAC1208 DAC1209 DAC1210 DAC1230 DAC1231 DAC1232 12-Bit mP Compatible ouble-Buffered D to A Converters
General Description
The DAC1208 and the DAC1230 series are 12-bit multiplying D to A converters designed to interface directly with a wide variety of microprocessors (8080 8048 8085 Z-80 etc ) Double buffering input registers and associated control lines allow these DACs to appear as a two-byte ``stack'' in the system's memory or I O space with no additional inT terfacing logic required he DAC1208 series provides all 12 input lines to allow single buffering for maximum throughput when used with 16-bit processors These input lines can also be externally configured to permit an 8-bit data interface The DAC1230 series can be used with an 8-bit data bus directly as it internally formulates the 12-bit DAC data from its 8 input lines All of T these DACs accept left-justified data from the processor he analog section is a precision silicon-chromium (Si-Cr) A R-2R ladder network and twelve CMOS current switches n inverted R-2R ladder structure is used with the binary weighted currents switched between the IOUT1 and IOUT2 maintaining a constant current in each ladder leg independent of the switch state Special circuitry provides TTL logic T input voltage level compatibility he DAC1208 series and DAC1230 series are the 12-bit members of a family of microprocessor compatible DACs (MICRO-DACsTM ) For applications requiring other resolutions the DAC1000 series for 10-bit and DAC0830 series for 8-bit are available alternatives
Y Y Y
eatures
Linearity specified with zero and full-scale adjust only Direct interface to all popular microprocessors Double-buffered single-buffered or flow through digital data inputs Logic inputs which meet TTL voltage level specs (1 4V logic threshold) Works with g 10V reference full 4-quadrant multiplication Operates stand-alone (without mP) if desired All parts guaranteed 12-bit monotonic DAC1230 series is pin compatible with the DAC0830 series 8-bit MICRO-DACs
Y
Y
Y Y Y
Key Specifications
Y Y Y
Y Y Y
Current Settling Time Resolution Linearity (Guaranteed over temperature) Gain Tempco Low Power Dissipation Single Power Supply
1 ms 12 Bits 10 11 or 12 Bits of FS 1 3 ppm C 20 mW 5 VDC to 15 VDC
F
Typical Application
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C
M I-STATE is a registered trademark of National Semiconductor Corp TR ICRO-DACTM is a trademark of National Semiconductor Corp
1995 National Semiconductor Corporation
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RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales ( Office Distributors for availability and specifications Notes 1 and 2) Supply Voltage (VCC) Voltage at Any Digital Input Voltage at VREF Input Storage Temperature Range Package Dissipation at TA e 25 C (Note 3) DC Voltage Applied to IOUT1 or IOUT2 (Note 4) ESD Susceptability
b 65
Operating Conditions
Lead Temperature (Soldering 10 sec ) 300 C Temperature Range TMIN s TA s TMAX DAC1208LCJ DAC1209LCJ DAC1210LCJ DAC1230LCJ DAC1231LCJ DAC1232LCJ b 40 C s TA s a 85 C DAC1231LIN DAC1232LIN DAC1208LCJ-1 DAC1210LCJ-1 DAC1230LCJ-1 DAC1231LCJ-1 DAC1232LCJ-1 DAC1231LCN DAC1232LCN DAC1231LCWM DAC1232LCWM 0 C s TA s a 70 C Range of VCC 4 75 VDC to 16 VDC VCC to GND Voltage at Any Digital Input
17 VDC VCC to GND
g 25V
C to a 150 C
500 mW
b 100 mV to VCC
800V
Electrical Characteristics
VREF e 10 000 VDC VCC e 11 4 VDC to 15 75 VDC unless otherwise noted Boldface limits apply from TMIN to TMAX (see Note 13) all other limits TA e TJ e 25 C T Parameter Resolution Linearity Error (End Point Linearity) Zero and Full-Scale Adjusted DAC1208 DAC1230 DAC1209 DAC1231 DAC1210 DAC1232 Zero and Full-Scale Adjusted DAC1208 DAC1230 DAC1209 DAC1231 DAC1210 DAC1232 Using Internal RFb Vref e g 10V g1V 4 7 13
g 0 018 g 0 024 g 0 050 g 0 018 g 0 024 g 0 05
Conditions
Notes
yp (Note 10) 12
Tested Limit (Note 5) 12
Design Limit (Note 6) 12
Units Bits
% of FSR % of FSR % of FSR
Differential Non-Linearity
4 7 13
g 0 018 g 0 024 g 0 050 g 0 018 g 0 024 g 0 05
% of FSR % of FSR % of FSR Bits % of FSR % of FSR
Monotonicity Gain Error (Min) Gain Error (Max) Gain Error Tempco Power Supply Rejection Reference Input Resistance (Min) Reference Input Resistance (Max) Output Feedthrough Error VREF e 20 Vp-p f e 100 kHz All Data Inputs Latched Low Output Capacitance All Data Inputs Latched High All Data Inputs Latched Low IOUT1 IOUT2 IOUT1 IOUT2 All Digital Inputs Latched High
4 7 7 7 7 13 9
12
b0 1 b0 1
g1 3 g3 0
12 00
b0 2
12
g6 0 g 30
ppm of FS C ppm of FSR V
15 15 30
10 20
10 20
kX mVp-p
200 70 70 200 13 20 01 01 15 15 08 22
b 200
pF pF pF pF mA nA nA VDC VDC mADC mADC
Supply Current Drain Output Leakage Current IOUT1 IOUT2 Digital Input Threshold Digital Input Currents All Data Inputs Latched Low All Data Inputs Latched High Low Threshold High Threshold Digital Inputs k0 8V Digital Inputs l2 2V
25 15 15 08 22
b 200
11 13 11 13 13 13 13 13
10
10
2
Electrical Characteristics (Continued) VREF e 10 000 VDC VCC e 11 4 VDC to 15 75 VDC unless otherwise noted Boldface limits apply from TMIN to TMAX (see Note 13) all other limits TA e TJ e 25 C S
Symbol Parameter Conditions ee Note Typ (Note 10) Tested Limit (Note 5) Design Limit (Note 6) Units
AC CHARACTERISTICS ts tW tDS tDH tCS tCH Current Setting Time Write and XFER Pulse Width Min Data Setup Time Min Data Hold Time Min Control Setup Time Min Control Hold Time Min VIL e 0V VIH e 5V VIL e 0V VIH e 5V VIL e 0V VIH e 5V VIL e 0V VIH e 5V VIL e 0V VIH e 5V VIL e 0V VIH e 5V 8 10 50 70 30 60 0 320 320 320 320 90 90 320 320 10 ns ms
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating N the device beyond its specified operating conditions Note 2 All voltages are measured with respect to GND unless otherwise specified ote 3 This 500 mW specification applies for all packages The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify N the power dissipation) removes concern for heat sinking ote 4 Both IOUT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier The linearity error is degraded by approximately VOS d VREF For Nxample if VREF e 10V then a 1 mV offset VOS on IOUT1 or IOUT2 will introduce an additional 0 01% linearity error e Note 5 Tested and guaranteed to National's AOQL (Average Outgoing Quality Level) ote 6 Design limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels Guaranteed for VCC e 11 4V to 15 75V Nnd VREF e b 10V to a 10V a ote 7 The unit FSR stands for full-scale range Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular VREF value to indicate the true performance of the part The Linearity Error specification of the DAC1208 is 0 012% of FSR(max) This guarantees that after performing a zero and full-scale adjustment the plot of the 4096 analog voltage outputs will each be within 0 012% c VREF of a straight line which passes through zero and full-scale The unit ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full-scale) are used for convenience to define specs of very small percentage values typical of higher accuracy converters In this instance 1 ppm of FSR e VREF 106 is the conversion factor to provide an actual output voltage quantity For example the gain error tempco spec of g 6 ppm of FS C represents a worst-case full-scale gain error change with temperature from b N 40 C to a 85 C of g (6)(VREF 106)(125 C) or g 0 75 (10b3) VREF which is g 0 075% of VREF ote 8 This spec implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tW) of 320 ns A typical part will operate with tW of only N00 ns The entire write pulse must occur within the valid data interval for the specified tW tDS tDH and tS to apply 1 Note 9 To achieve this low feedthrough in the D package the user must ground the metal lid If the lid is left floating the feedthrough is typically 6 mV Note 10 Typicals are at 25 C and represent the most likely parametric norm Note 11 A 10 nA leakage current with RFb e 20k and VREF e 10V corresponds to a zero error of (10 c 10b9 c 20 c 103) c 100% 10V or 0 002% of FS Note 12 Human body model 100 pF discharged through a 1 5 kX resistor o Cte 13 Tested limit for b 1 suffix parts applies only at 25 C
onnection Diagrams
Dual-In-Line Package Dual-In-Line Package
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See Ordering Information 3
Switching Waveforms
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Typical Performance Characteristics
Digital Input Threshold vs VCC Digital Input Threshold vs Temperature Gain and Linearity Error Variation vs Temperature
Gain and Linearity Error Variation vs Supply Voltage
Control Set-Up Time tCS
Data Hold Time tDH
Write Pulse Width tW
Data Set-Up Time tDS
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4
Definition of Package Pinouts
CONTROL SIGNALS (all control signals are level actuated) W Chip Select (active low) The CS will enable WR1 CS R1 Write 1 The active low WR1 is used to load the digital data bits (DI) into the input latch The data in the input latch is latched when WR1 is high The 12-bit input latch is split into two latches One holds the first 8 bits while the other holds 4 bits The Byte 1 Byte 2 control pin is used to select both latches when Byte 1 Byte 2 is high or to overwrite the B 4-bit input latch when in the low state yte 1 Byte 2 Byte Sequence Control When this control is high all 12 locations of the input latch are enabled When low only the four least significant locations of the input latch W are enabled X R2 Write 2 (active low) The WR2 will enable XFER FER Transfer Control Signal (active low) This signal in combination with WR2 causes the 12-bit data which is D available in the input latches to transfer to the DAC register I0 to DI11 Digital Inputs DI0 is the least significant digital input (LSB) and DI11 is the most significant digital input I (MSB)
OUT1 DAC Current Output 1 IOUT1 is a maximum for a digital code of all 1s in the DAC register and is zero for all I 0s in the DAC register OUT2 DAC Current Output 2 IOUT2 is a constant minus IOUT1 or IOUT1 a IOUT2 e constant (for a fixed reference voltage) This constant current is
the DAC1230 DAC1231 and DAC1232 must be connected to ground It is important that IOUT1 and IOUT2 are at ground potential for current switching applications Any difference of potential (VOS on these pins) will result in a linearity change of VOS 3 VREF For example if VREF e 10V and these ground pins are 9 mV offset from IOUT1 and IOUT2 the linearity change will be 0 03%
Definition of Terms
Resolution Resolution is defined as the reciprocal of the number of discrete steps in the DAC output It is directly related to the number of switches or bits within the DAC For example the DAC1208 has 212 or 4096 steps and therefore L has 12-bit resolution inearity Error Linearity error is the maximum deviation from a straight line passing through the endpoints of the DAC transfer characteristic It is measured after adjusting for zero and full-scale Linearity error is a parameter intrinsic N to the device and cannot be externally adjusted ational's linearity test (a) and the best straight line test (b) used by other suppliers are illustrated below The best straight line (b) requires a special zero and FS adjustment for each part which is almost impossible for the user to determine The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for P DAC linearity ower Supply Sensitivity Power supply sensitivity is a measure of the effect of power supply changes on the DAC S full-scale output ettling Time Full-scale current settling time requires zero to full-scale or full-scale to zero output change Settling time is the time required from a code transition until the DAC o Futput reaches within g LSB of the final output value ull-Scale Error Full-scale error is a measure of the output I error between an ideal DAC and the actual device output deally for the DAC1208 or DAC1230 series full-scale is VREFb1 LSB For VREF e 10V and unipolar operation FULL-SCALE e 10 0000V b 2 44 mV e 9 9976V Full-scale D error is adjustable to zero ifferential Non-Linearity The difference between any two consecutive codes in the transfer curve from the theoM retical 1 LSB is differential non-linearity onotonic If the output of a DAC increases for increasing digital input code then the DAC is monotonic A 12-bit DAC which is monotonic to 12 bits simply means that input increasing digital input codes will produce an increasing analog output T
1 4096 R divided by the reference input resistance Fb Feedback Resistor The feedback resistor is provided on the IC chip for use as the shunt feedback resistor for the external op amp which is used to provide an output voltage for the DAC This on-chip resistor should always be used (not an external resistor) since it matches the resistors in the on-chip R-2R ladder and tracks these resistors over V temperature VREF c
b
REF Reference Voltage Input This input connects an exV ternal precision voltage source to the internal R-2R ladder REF can be selected over the range of 10V to b 10V This is also the analog voltage input for a 4-quadrant multiplying V DAC application CC Digital Supply Voltage This is the power supply pin for the part VCC can be from 5 VDC to 15 VDC Operation is optimum for 15 VDC G
1
J
ND Pins 3 and 12 of the DAC1208 DAC1209 and DAC1210 must be connected to ground Pins 3 and 10 of
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a) End Point Test After Zero and FS Adjust 5
b) Shifting FS Adjust to Pass Best Straight Line Test
Others parts begin by da
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