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Part: 11C06
Category:
Logic
-> Flip-Flops
Description: 750 MHZ D-type Flip-flop (obsolete)
Company: National Semiconductor Corporation
Datasheet: Download 11C06 datasheet File size : 267 kB
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Datasheet text preview:
11C06 750 MHz D-Type Flip-Flop
Not Intended For New Designs
August 1992
11C06 750 MHz D-Type Flip-Flop
General Description
The 11C06 is a high-speed ECL D-Type Master-Slave FlipFlop capable of toggle rates over 750 MHz Designed primarily for high-speed prescaling it can also be used in any application which does not require preset inputs The circuit is voltage-compensated which makes input thresholds and L output levels insensitive to VEE variations Complementary Q and Q outputs are provided as are two Data inputs Clock and Clock Enable inputs The 11C06 is pin-compatible with the Motorola MC1690L but is a higher-frequency replacement
ogic Symbol
Connection Diagrams
16-Pin DIP 16-Pin Flatpak
TL F 9890 3 TL F 9890 2 TL F 9890 1
Truth Table
Pin Names Dn CP CE QQ Description Data Input Clock Input Clock Enable (Active LOW) Outputs CE L L L L H CP L H L L X D X X L H X Qn Qnb1 Qnb1 L H Qnb1
H e HIGH Voltage Level L e LOW Voltage Level X e Don't Care L e LOW to HIGH Transition Qnb1 e Previous State
C1995 National Semiconductor Corporation
TL F 9890
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
Above which the useful life may be impaired p If Military Aerospace specified devices are required lease contact the National Semiconductor Sales S Office Distributors for availability and specifications torage Temperature Maximum Junction Temperature (TJ) Supply Voltage Range Input Voltage (DC) Output Current (DC Output HIGH)
b 65
Operating Range Lead Temperature (Soldering 10 sec )
b 5 7V to b 4 7V
300 C
C to a 150 C a 150 C
VEE to GND b 50 mA
b 7 0V to GND
Recommended Operating Conditions
Min Supply Voltage (VEE) Ambient Temperature (TA)
b 5 7V
Typ
b 5 2V
Max
b 4 7V a 75 C
0C
DC Electrical Characteristics
VEE e b5 2V VCC e GND Symbol VOH Parameter Output Voltage HIGH Min
b 1000 b 960 b 900 b 1870 b 1850 b 1830 b 1020 b 980 b 920 b 1615 b 1600 b 1575 b 1135 b 1095 b 1035 b 1870 b 1850 b 1830 b 840 b 810 b 720 b 1500 b 1485 b 1460
Typ
Max
b 840 b 810 b 720 b 1635 b 1620 b 1595
Units mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mA mA mA
TA 0C a 25 C a 75 C 0C
a 25 a 75
Conditions VIN e VIH (Max) or VIL (Min) per Truth Table Loading 50X to b2V
VOL
Output Voltage LOW
C C C C C C C C C C C C C C
VIN e VIH (Min) All Inputs Open Guaranteed Input Voltage HIGH for All Inputs Guaranteed Input Voltage LOW for All Inputs VIN e VIH (Max) VIN e VIH (Min) or VIL (Max) for Dn Inputs Loading 50X to b2V
VOHC
Output Voltage HIGH
0C
a 25 a 75
VOLC
Output Voltage LOW
0C
a 25 a 75
VIH
Input Voltage HIGH
0C
a 25 a 75
VIL
Input Voltage LOW
0C
a 25 a 75 a 25 a 25 a 25 a 25
IIH
Input Current HIGH Clock Input Data Input Input Current LOW Power Supply Current 05
b 59 b 40
250 270
IIL IEE
mA
AC Electrical Characteristics
VEE e b5 2V VCC e GND TA e a 25 C Symbol tPHL tPLH tTLH tTHL tS tH fTOG (MAX) Parameter Propagation Delay (CP-Q) Propagation Delay (CP-Q) Transition Time 20% to 80% Transition Time 80% to 20% Set-up Time Hold Time Toggle Frequency (CP) 650 Min 07 07 05 05 Typ 10 10 08 08 02 02 750 Max 12 12 10 10 Units ns ns ns ns ns ns MHz See Figure 2 Note See Figure 1 Conditions
Note The device is guaranteed for fTOG (CP) t 600 MHz fTOG(CE) t 550 MHz over the 0 C to a 75 C temperature range 2
Functional Description
While the clock is LOW the slave is held steady and the T information on the D input is permitted to enter the master he next transition from LOW to HIGH locks the master in its present state making it insensitive to the D input This transition simultaneously connects the slave to the master causing the new information to appear on the outputs Master and slave clock thresholds are internally offset in opposite directions to avoid race conditions or simultaneous master-slave changes when the clock has slow rise or fall T times he CP and CE inputs are logically identical but physical constraints associated with the Dual-In-Line package make the CE input slower at the upper end of the toggle range To prevent new data from entering the master on the next CP LOW cycle CE should go HIGH while CP isTstill HIGH
L F 9890 4
RT e 50X termination of scope L1 e 50X impedance lines All input transition times are 2 0 ns g 0 2 ns
FIGURE 1 Propagation Delay (CP to Q)
RT e 50X termination of scope L1 e 50X impedance lines Adjust VBIAS for a 0 7V baseline of A 800 mV peak-to-peak sinewave input ll input transition times are 2 0 ns g 0 2 ns
TL F 9890 5
FIGURE 2 Toggle Frequency Test Circuit
3
Typical Waveforms
TL F 9890 6
Horizontal Scale e 1 0 ns div Vertical Scale e 200 mV div
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 1
1C06 Device Number (basic) Package Code D e Ceramic Dual-In-Line F e Flatpak
D
C
QR Special Variations QR e Commercial grade device with burn-in Temperature Range C e Commercial (0 C to a 85 C)
4
Physical Dimensions inches (millimeters)
16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A
5
Others parts begin by 11
11-1 11-2 11-3
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