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Part: 100331WFQMLV
Category:
Description:
Company: National Semiconductor Corporation
Datasheet: Download 100331WFQMLV datasheet File size : 369 kB
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100331 Low Power Triple D Flip-Flop
August 1998
100331 Low Power Triple D Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 k pull-down resistors.
Features
n n n n n n 35% power reduction of the 100131 2000V ESD protection Pin/function compatible with 100131 Voltage compensated operating range = -4.2V to -5.7V Available to industrial grade temperature range Available to Standard Microcircuit Drawing (SMD) 5962-9153601
Logic Symbol
Pin Names CP0 CP2 CPC D0 D2 CD0 CD2 SDn MR MS Q0-Q2 Q0 Q2
DS100300-1
Description Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs
Connection Diagrams
24-Pin DIP 24-Pin Quad Cerpak
DS100300-3 DS100300-2
© 1998 National Semiconductor Corporation
DS100300
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Logic Diagram
DS100300-5
Truth Tables Synchronous Operation
(Each Flip-Flop) Inputs Dn L H L H X X X CPn
N N
Asynchronous Operation
(Each Flip-Flop) Inputs Dn Outputs MS SDn L L L L L L L MR CDn L L L L L L L L H L H Qn(t) Qn(t) Qn(t) Qn(t + 1) X X X X X X X X X CPn CPC MS SDn H L H MR CDn L H H H L U Outputs Qn(t + 1)
CPC L L
N N
L L L H X
L X H
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care U = Undefined t = Time before CP Positive Transition t + 1 = Time after CP Positive Transition N = LOW to HIGH Transition
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Above which the useful life may be impaired -65°C to +150°C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic +175°C Pin Potential to -7.0V to +0.5V Ground Pin (VEE)
Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2)
VEE to +0.5V -50 mA 2000V
Recommended Operating Conditions
Case Temperature (TC) Military Supply Voltage (VEE) -55°C to +125°C -5.7V to -4.2V
Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version DC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -55°C to +125°C Symbol VOH Parameter Output HIGH Voltage Min -1025 -1085 VOL Output LOW Voltage -1830 -1830 VOHC Output HIGH Voltage -1035 -1085 VOLC Output LOW Voltage -1610 -1555 VIH VIL IIL IIH Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current -1165 -1830 0.50 240 340 IEE Power Supply Current -130 -50 -870 -1475 Max -870 -870 -1620 -1555 Units mV mV mV mV mV mV mV mV mV mV µA µA µA mA TC 0°C to +125°C -55°C 0°C to +125°C -55°C 0°C to +125°C -55°C 0°C to +125°C -55°C -55°C to +125°C -55°C to +125°C -55°C to +125°C 0°C to +125°C -55°C -55°C to +125°C Inputs Open (Notes 3, 4, 5) Guaranteed HIGH Signal for all Inputs Guaranteed LOW Signal for all Inputs VEE = -4.2V VIN = VIL (Min) VEE = -5.7V VIN = VIH (Max) (Notes 3, 4, 5, 6) (Notes 3, 4, 5, 6) (Notes 3, 4, 5) (Notes 3, 4, 5) VIN = VIH (Min) or VIL (Max) Loading with 50 to -2.0V (Notes 3, 4, 5) Conditions VIN = VIH (Max) or VIL (Min) Loading with 50 to -2.0V Notes (Notes 3, 4, 5)
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Note 4: Screen tested 100% on each device at -55°C, +25°C, and +125°C, Subgroups, 1, 2, 3, 7 and 8. Note 5: Sampled tested (Method 5005, Table I) on each manufactured lot at -55°C, +25°C, and +125°C, Subgroups A1, 2, 3, 7 and 8. Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
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AC Electrical Characteristics
VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL ts Transition Time 20% to 80%, 80% to 20% Setup Time Dn CDn, SDn (Release Time) MS, MR (Release Time) th tpw(H) Hold Time Dn Pulse Width HIGH CPn, CPC, CDn, SDn, MR, MS
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Note 8: Screen tested 100% on each device at +25°C. Temperature only, Subgroup A9. Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25°C, Subgroup A9, and at +125°C, and -55°C Temp., Subgroups A10 and A11. Note 10: Not tested at +25°C, +125°C and -55°C Temperature (design characterization data).
Parameter Toggle Frequency Propagation Delay CPC to Output Propagation Delay CPn to Output Propagation Delay CDn, SDn to Output
TC = -55°C Min 400 0.50 0.50 0.50 0.50 2.20 2.20 2.20 2.40 2.70 2.90 1.40 Max
TC = +25°C Min 400 0.60 0.60 0.60 0.60 0.80 0.80 0.20 2.00 2.00 2.00 2.10 2.60 2.80 1.40 Max
TC = +125°C Min 400 0.50 0.50 0.50 0.50 0.80 0.80 0.20 2.40 2.40 2.40 Max
Units MHz ns
Conditions
Notes (Note 10)
Figures 2, 3
Figures 1, 3
ns CPn, CPC = L ns 2.50 2.90 ns 0.70 0.20 3.10 1.40 ns CPn, CPC = H CPn, CPC = H CPn, CPC = L
Figures 1, 4
(Notes 7, 8, 9)
Propagation Delay MS, MR to Output
0.70
Figures 1, 3, 4 Figure 5
1.00 1.50 2.50 1.50 2.00
0.80 1.30 2.30 1.30 2.00
0.90 1.60 2.50 1.60 2.00 ns ns ns
Figure 4 Figure 5 Figures 3, 4
(Note 10)
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Test Circuits
DS100300-6
FIGURE 1. AC Test Circuit
DS100300-7
Notes: VCC, VCCA = +2V, VEE = -2.5V L1 and L2 = Equal length 50 impedance lines RT = 50 terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50 to GND CL = Fixture and stray capacitance 3 pF
FIGURE 2. Toggle Frequency Test Circuit
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