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Part: M2S28D40ATP-75
Category:
Memory
-> DRAM
-> DDR SDRAM
-> 128 Mb
Description:
Company: Mitsubishi Electronics America, Inc.
Datasheet: Download M2S28D40ATP-75 datasheet File size : 41 kB
Request For quote: Find where to buy M2S28D40ATP-75
Datasheet text preview:
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge controlled by A10 - 4096 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-11 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - SSTL_2 Interface - 400-mil, 66-pin Thin Small Outline Package (TSOP II) - FET switch control(/QFC) for x4/ x8 - JEDEC standard
MITSUBISHI ELECTRIC
1
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM PIN CONFIGURATION(TOP VIEW)
x4 x8 x16
VD D NC VD DQ NC DQ 0 VSSQ NC NC VD DQ NC DQ 1 VSSQ NC NC VD DQ NC NC VD D NU ,/QFC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VD D VD D DQ 0 VD DQ NC DQ 1 VSSQ NC DQ 2 VD DQ NC DQ 3 VSSQ NC NC VD DQ NC NC VD D NU ,/QFC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VD D VD D DQ 0 VD DQ DQ 1 DQ 2 VSSQ DQ 3 DQ 4 VD DQ DQ 5 DQ 6 VSSQ DQ 7 NC VD DQ LDQ S NC VD D NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VD D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ 15 VSSQ DQ 14 DQ 13 VD DQ DQ 12 DQ 11 VSSQ DQ 10 DQ 9 VD DQ DQ 8 NC VSSQ UD QS NC VR EF VSS UD M /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ 7 VSSQ NC DQ 6 VD DQ NC DQ 5 VSSQ NC DQ 4 VD DQ NC NC VSSQ DQ S NC VR EF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ 3 VD DQ NC NC VSSQ NC DQ 2 VD DQ NC NC VSSQ DQ S NC VR EF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
66pin TSOP(II)
400mil width x 875mil length 0.65mm Lead Pitch
ROW A0-11 Column A0-9,11(x4) A0-9 (x8) A0-8 (x16)
CLK,/CLK CKE /CS /RA S /CA S /WE DQ0-7 DQS DM /QFC Vr ef
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Data Strobe : Write Mask : FET Switch Control for x4/x8 : Reference Voltage
A0 - 1 1 BA0,1 Vdd VddQ Vs s VssQ
: Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output
MITSUBISHI ELECTRIC
2
DDR SDRAM (Rev.0.1) Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
BLOCK DIAGRAM
DLL
DQ0 - 15
/QFC for x4/x8 UDQS,LDQS
I/O Buffer
QFC&QS Buffer
Memory Array Bank #0
Memory Array Bank #1
Memory Array Bank #2
Memory Array Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer A0-11 BA0,1 CLK, /CLK CKE
Control Signal Buffer
/CS /RAS /CAS /WE
UD M , LDM
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 2 S 28 D 3 0 A TP -75
Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0 75: 133MHz@CL=2.5,100MHz@CL=2.0 Package Type TP: TSOP(II) Process Generation Function Reserved for Future Use Organization 2 n 2: x4, 3: x8, 4: x16 D DR Synchronous DRAM Density 28: 128M bits Interface V:LVTTL, S:SSTL_3, _2 Memory Style (DRAM) Mitsubishi Main Designation
MITSUBISHI ELECTRIC
3
Others parts begin by m2
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