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Part: MAX7310
Category:
Microcontrollers
Description: MAX7310 2-Wire-Interfaced 8-Bit I/o Port Expander With Reset
Company: Maxim Integrated Products
Datasheet: Download MAX7310 datasheet File size : 502 kB
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Datasheet text preview:
19-2698; Rev 0; 1/03
2-Wire-Interfaced 8-Bit I/O Port Expander with Reset
General Description
The MAX7310 provides 8-bit parallel input/output port expansion for SMBusTM-compatible and I2C-compatible applications. The MAX7310 consists of an input port register, an output port register, a polarity inversion register, a configuration register, a bus timeout register, and an SMBus/I2C-compatible serial interface. The system master can invert the MAX7310 input data by writing to the active-high polarity inversion register. The system master can enable or disable bus timeout by writing to the bus timeout register. Any of the eight I/O ports may be configured as input or output. An active-low reset input sets the eight I/Os as inputs. Three address select pins configure one of 56 slave ID addresses. The MAX7310 is available in 16-pin thin QFN, TSSOP, and QSOP packages and is specified over the -40°C to +125°C automotive temperature range. o 400kHz 2-Wire Interface o 2.3V to 5.5V Operation o Low Standby Current (1.7µA typ) o Bus Timeout for Lock-Up-Free Operation o 56 Slave ID Addresses o Polarity Inversion o Eight I/O Pins that Default to Inputs on Power-Up o 5V Tolerant Open-Drain Output on I/O0 o 4mm x 4mm, 0.8mm Thin QFN Package o -40°C to +125°C Operation
Features
MAX7310
Applications
Servers RAID Systems Industrial Control Medical Equipment Instrumentation, Test Measurement
PART MAX7310AUE MAX7310AEE MAX7310ATE
Ordering Information
TEMP RANGE -40°C to +125°C -40°C to +125°C -40°C to +125°C PIN-PACKAGE 16 TSSOP 16 QSOP 16 Thin QFN
SMBus is a trademark of Intel Corp.
Pin Configurations
SDA V+ 14
TOP VIEW
SCL 1 SDA 2 AD0 3 AD1 4 AD2 5 I/O0 6 I/O1 7 GND 8 16 V+ 15 RESET 14 I/O7 13 I/O6 AD1 AD2 I/O0 2 3 4 AD0 1
16
15
SCL
13
RESET
12 I/O7 11 I/O6 10 I/O5 9 I/O4 8 I/O3
MAX7310
12 I/O5 11 I/O4 10 I/O3 9 I/O2
MAX7310
5 I/01
6 GND
7 I/O2
TSSOP/QSOP
THIN QFN
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2-Wire-Interfaced 8-Bit I/O Port Expander with Reset MAX7310
ABSOLUTE MAXIMUM RATINGS
V+ to GND .......-0.3V to +6V I/O1I/O7 as an Input .....(VSS - 0.3V) to (VDD + 0.3V) I/O0 as an Input....(VSS - 0.3V) to +6V SCL, SDA, AD0, AD1, AD2, RESET ......(VSS - 0.3V) to +6V DC Current on I/O0 ........ +400µA DC Current on I/O1 to I/O7 ............ ±50mA Maximum GND and V+ Current.......180mA Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 5.7mW/°C above +70°C) .........457mW 16-Pin QSOP (derate 8.3mW/°C above +70°C)..667mW 16-Pin Thin QFN (derate 16.9mW/°C above +70°C) ...1349mW Operating Temperature Range .......-40°C to +125°C Junction Temperature ......+150°C Storage Temperature Range .....-65°C to +150°C Lead Temperature (soldering, 10s) .........+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1)
PARAMETER Supply Voltage Supply Current SYMBOL V+ I+ All outputs floating, all inputs at V+ or GND, fSCL = 400kHz All outputs floating, all inputs at V+ or GND, fSCL = 0 V+ = 2.3V V+ = 3.3V V+ = 5.5V V+ = 2.3V V+ = 3.3V V+ = 5.5V CONDITIONS MIN 2.3 19 29 65 1.5 1.7 2.1 1.6 VIL VIH V OIL IL CI VIL VIH IL IOL All inputs at V+ or GND V+ = 2.3V, VOL = 0.5V Low-Level Output Current V+ = 3.3V, VOL = 0.5V V+ = 5.5V, VOL = 0.5V High Output Current for I/O1I/O7 AD0, AD1, AD2, AND RESET Input Voltage Low Input Voltage High 2 0.8 V V IOH V+ = 3.3V, VOH = 2.4V V+ = 5.5V, VOH = 4.5V 2 -1 8 12.5 19 6.5 12.5 14 22 30 11 18 mA mA +1 ISINK = 6mA -1 10 0.8 2 0.4 +1 TYP MAX 5.5 30 40 80 3.4 3.9 5 2.1 0.8 V V V V µA pF V V µA µA µA UNITS V
Standby Current Power-On Reset Voltage SCL, SDA Input Voltage Low Input Voltage High Low-Level Output Voltage Leakage Current Input Capacitance I/Os Input Voltage Low Input Voltage High Input Leakage Current
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2-Wire-Interfaced 8-Bit I/O Port Expander with Reset
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1)
PARAMETER Leakage Current Input Capacitance SYMBOL CONDITIONS MIN -1 10 TYP MAX +1 UNITS µA pF
MAX7310
AC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER SCL Clock Frequency BUS Timeout Bus Free Time Between STOP and START Condition Hold Time (Repeated) START Condition Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Low Period SCL High Period SCL/SDA Fall Time (Transmitting) Pulse Width of Spike Supressed PORT TIMING Output Data Valid Input Data Setup Time Input Data Hold Time RESET Reset Pulse Width 100 ns tPV tPS tPH Figure 9 Figure 10 Figure 10 29 0 1 µs µs µs SYMBOL fSCL t TIMEOUT tBUF tHD, STA tSU, STA tSU, STO tHD, DAT tSU, DAT tL O W tH I G H tF tSP Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 (Note 3) Figure 2 Figure 2 Figure 2 Figure 2 (Note 4) (Note 5) 50 0.1 1.3 0.7 250 (Note 2) 30 1.3 0.6 0.6 0.6 0.9 CONDITIONS MIN TYP MAX 400 60 UNITS kHz ms µs µs µs µs µs µs µs µs ns ns
Note 1: All parameters are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design. Note 2: Minimum SCL clock frequency is limited by the MAX7310 bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for a 30ms minimum. Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge. Note 4: tF measured between 90% to 10% of V+. Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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