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Part: MAX5887EGK
Category:
Data Conversion
-> DAC (Digital to Analog Converters)
Description: MAX5887 3.3V, 14-Bit, 500Msps High Dynamic Performance DAC With Differential LVDS Inputs
Company: Maxim Integrated Products
Datasheet: Download MAX5887EGK datasheet File size : 524 kB
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Datasheet text preview:
19-2777; Rev 0; 4/03
3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
General Description
The MAX5887 is an advanced, 14-bit, 500Msps digitalt o - a n a l o g converter (DAC) designed to meet the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from a single 3.3V supply, this DAC offers exceptional dynamic performance such as 76dBc spurious-free dynamic range (SFDR) at f OUT = 30MHz. The DAC supports update rates of 500Msps and a power dissipation of only 230mW. The MAX5887 utilizes a current-steering architecture, which supports a full-scale output current range of 2mA to 20mA, and allows a differential output voltage swing between 0.1VP-P and 1VP-P. The MAX5887 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy and low noise performance. Additionally, a separate reference input pin enables the user to apply an extern a l reference source for optimum flexibility and to improve gain accuracy. The digital and clock inputs of the MAX5887 are designed for differential low-voltage differential signal ( L V D S ) - c o m p a t i b l e voltage levels. The MAX5887 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended industrial temperature range (-40°C to +85°C). Refer to the MAX5886 and MAX5888 data sheets for pin-compatible 12- and 16-bit versions of the MAX5887. 500Msps Output Update Rate Single 3.3V Supply Operation Excellent SFDR and IMD Performance SFDR = 76dBc at fOUT = 30MHz (to Nyquist) IMD = -85dBc at fOUT = 10MHz ACLR = 72dB at fOUT = 61MHz 2mA to 20mA Full-Scale Output Current Differential, LVDS-Compatible Digital and Clock Inputs On-Chip 1.2V Bandgap Reference Low 130mW Power Dissipation 68-Lead QFN-EP Package
Features
MAX5887
Ordering Information
PART TEMP RANGE PIN-PACKAGE 68 QFN-EP* MAX5887EGK -40°C to +85°C *EP = Exposed paddle.
Pin Configuration
DGND DGND DVDD B2N B3N B4N B5N B6N B7N B2P B3P B5P B6P B4P B7P B8P
51 B9N 50 B9P 49 B10N 48 B10P 47 B11N 46 B11P 45 B12N 44 B12P 43 B13N 42 B13P 41 DGND 40 DVDD 39 SEL0 38 N.C. 37 N.C. 36 N.C. 35 N.C.
TOP VIEW
Applications
Base Stations: Single-/Multicarrier UMTS, CDMA, GSM Communications: LMDS, MMDS, Point-to-Point Microwave Digital Signal Synthesis Automated Test Equipment (ATE) Instrumentation
B1P B1N B0P B0N N.C N.C N.C N.C DGND
1 2 3 4 5 6 7 8 9
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52
MAX5887
DVDD 10 VCLK 11 CLKGND 12 CLKP 13 CLKN 14 CLKGND 15 VCLK 16 PD 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AGND
REFIO
AVDD
AVDD
AVDD
AVDD
IOUTN
FSADJ
DACREF
IOUTP
AGND
AVDD
N.C.
B8N AGND
AGND
QFN
________________________________________________________________ Maxim Integrated Products
AGND
N.C.
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs MAX5887
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD, VCLK to AGND........-0.3V to +3.9V AVDD, DVDD, VCLK to DGND .......-0.3V to +3.9V AVDD, DVDD, VCLK to CLKGND ...-0.3V to +3.9V AGND, CLKGND to DGND...-0.3V to +0.3V DACREF, REFIO, FSADJ to AGND....-0.3V to AVDD + 0.3V IOUTP, IOUTN to AGND........-1V to AVDD + 0.3V CLKP, CLKN to CLKGND...-0.3V to VCLK + 0.3V B0P/B0NB13P/B13N, SEL0, PD to DGND ..........-0.3V to DVDD + 0.3V Continuous Power Dissipation (TA = +70°C) 68-Pin QFN-EP (derate 41.7mW/°C above +70°C) ......3333mW Thermal Resistance (JA) ....+24°C/W Operating Temperature Range ..-40°C to +85°C Junction Temperature .....+150°C Storage Temperature Range ....-60°C to +150°C Lead Temperature (soldering, 10s) ........+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO = 1.25V, RL = 50, IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. +25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Drift Full-Scale Gain Error Gain Drift Full-Scale Output Current Min Output Voltage Max Output Voltage Output Resistance Output Capacitance DYNAMIC PERFORMANCE Output Update Rate Noise Spectral Density Spurious-Free Dynamic Range to Nyquist fCLK fCLK = 100MHz fCLK = 200MHz SFDR fCLK = 100MHz fOUT = 16MHz, -12dB FS fOUT = 80MHz, -12dB FS fOUT = 1MHz, 0dB FS fOUT = 1MHz, -6dB FS fOUT = 1MHz, -12dB FS 1 -157 -157 88 89 80 dBc 500 Msps dB FS/ Hz ROUT C OUT IOUT GEFS External reference, TA +25°C Internal reference External reference (Note 1) Single ended Single ended 2 -0.5 1.1 1 5 -3.5 ±100 ±50 20 INL DNL OS Measured differentially Measured differentially -0.025 14 ±0.8 ±0.5 ±0.01 ±50 +1.5 +0.025 Bits LSB LSB % FS ppm/°C % FS ppm/°C mA V V M pF SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V REFIO = 1.25V, RL = 50, IOUT = 20mA, TA = TMIN to TMAX, unless otherwise noted. +25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS fCLK = 100MHz fOUT = 10MHz, -12dB FS fOUT = 30MHz, -12dB FS fOUT = 10MHz, -12dB FS fCLK = 200MHz SFDR fOUT = 16MHz, -12dB FS, TA +25°C fOUT = 50MHz, -12dB FS fOUT = 80MHz, -12dB FS fOUT = 10MHz, -12dB FS fCLK = 500MHz fOUT = 30MHz, -12dB FS fOUT = 50MHz, -12dB FS fOUT = 80MHz, -12dB FS fCLK = 100MHz 2-Tone IMD TTIMD fCLK = 200MHz 4-Tone IMD, 1MHz Frequency Spacing, GSM Model Adjacent Channel Leakage Power Ratio, 4.1MHz Bandwidth, WCDMA Model Output Bandwidth REFERENCE Internal Reference Voltage Range Reference Voltage Drift Reference Input Compliance Range Reference Input Resistance ANALOG OUTPUT TIMING Output Fall Time Output Rise Time Output Voltage Settling Time Output Propagation Delay Glitch Energy Output Noise TIMING CHARACTERISTICS Data to Clock Setup Time Data to Clock Hold Time tS E T U P tH O L D Referenced to rising edge of clock (Note 4) Referenced to rising edge of clock (Note 4) -0.8 1.8 ns ns N OUT IOUT = 2mA IOUT = 20mA tFALL tR I S E tSETTLE tPD 90% to 10% (Note 3) 10% to 90% (Note 3) Output settles to 0.025% FS (Note 3) (Note 3) 375 375 11 1.8 1 30 30 ps ps ns ns pV-s pA/Hz V REFIO TCOREF V REFIOCR RREFIO 0.1 10 1.12 1.22 ±50 1.25 1.32 V ppm/°C V k FTIMD fCLK = 300MHz fCLK = 184.32MHz (Note 2) fOUT1 = 9MHz, -6dB FS, fOUT2 = 10MHz, -6dB FS fOUT1 = 79MHz, -6dB FS, fOUT2 = 80MHz, -6dB FS fOUT = 32MHz, -12dB FS 69 MIN TYP 81 76 71 76 72 64 66 63 65 59 -85 dBc -61 -78 dBc dBc MAX UNITS
MAX5887
Spurious-Free Dynamic Range to Nyquist
ACLR BW-1dB
fOUT = 61.44MHz
72 450
dB MHz
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