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Part: MAX555CCB
Category:
Data Conversion
-> High-Speed Data Converters
Description: MAX555 300Msps, 12-Bit DAC With Complementary Voltage Outputs
Company: Maxim Integrated Products
Datasheet: Download MAX555CCB datasheet File size : 407 kB
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Datasheet text preview:
19-0297; Rev 3; 6/02
NUAL KIT MA UATION BLE EVAL AVAILA
300Msps, 12-Bit DAC with Complementary Voltage Outputs
____________________________Features
o 12-Bit Resolution o ฑ1/2LSB Integral and Differential Nonlinearity o Capable of 300Msps (min) Update Rate o Complementary 50 Outputs o Multiplying Reference Input o Low Glitch Energy (5.6pVs) o Single -5.2V Power Supply o On-Chip Data Registers o ECL-Compatible Inputs with Differential Clock
General Description
The MAX555 is an advanced, monolithic, 12-bit digitalto-analog converter (DAC) with complementary 50 o u t p u t s . Fabricated using an oxide-isolated bipolar process, the MAX555 is designed for signal-reconstruction applications at an output update rate of 300Msps. I t incorporates an analog multiplying function with 10MHz useable input bandwidth. The voltage-output DAC uses precision laser trimming to achieve 12-bit accuracy with ฑ1/2LSB integral and differential linearity (ฑ0.012% FS). Absolute gain error is a low 1% of full scale. Full-scale transitions occur in less than 0.5ns. Internal registers and a unique decoder reduce glitching and allow the MAX555 to achieve precise RF performance with over 73dBc of spurious-free dynamic range at 50Msps with fOUT = 3.1MHz, or 62dBc at 300Msps with fOUT = 18.6MHz. The MAX555 operates from a single -5.2V supply and dissipates 980mW (nominal). It comes in a 64-pin TQFP package with exposed paddle for enhanced thermal dissipation.
MAX555
Ordering Information
PART MAX555CCB TEMP RANGE 0ฐC to +70ฐC PIN-PACKAGE 64 TQFP-EP*
________________________Applications
Direct Digital Synthesis Arbitrary Waveform Generation HDTV/High-Resolution Graphics Instrumentation Communications Local Oscillators Automated Tester Applications
*EP = Exposed pad. Pin Configuration appears at end of data sheet.
___________________________________________________Simplified Block Diagram
CLK CLK 800
MAX555
LEVEL-SENSITIVE TRANSPARENT LATCH 800
REF
ROFFSET VOUT
12-BIT ECL LINES
DECODED BIT LINES 50 -20mA 50
VOUT
LGND AVEE BYPASS
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
300Msps, 12-Bit DAC with Complementary Voltage Outputs MAX555
ABSOLUTE MAXIMUM RATINGS
Analog Supply Voltage (AVEE) .........-7V to +0.3V Digital Supply Voltage (DVEE) ..........-7V to +0.3V Digital Input Voltage (D0ญD11) ..-5.5V to 0V Reference Input Voltage (VIN) .........0V to +1.25V Reference Input Current...0mA to +1.56mA Output Compliance Voltage (VOC) ....-1.25V to +1.0V Output Common-Mode Voltage (VCM) .......-0.25V to +1.0V Continuous Power Dissipation (TA = +70ฐC) (without additional heatsink) ....1.3W Operating Temperature Range.......0ฐC to +70ฐC Junction Temperature Range (Note 1) ........0ฐC to +150ฐC Storage Temperature Range .....-65ฐC to +150ฐC Lead Temperature (soldering, 10s) .........+300ฐC
Note 1: Typical thermal resistance, junction-to-case RJC = 25ฐC/W. See Package Information.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVEE = DVEE = -5.2V, VREF = 1.000V, TMIN to TMAX = 0ฐC to +70ฐC, unless otherwise noted.) (Note 2.) PARAMETER DC ACCURACY Differential Linearity Error Integral Linearity Error Absolute Gain Error 12-Bit Monotonicity Output Offset Current Output Leakage Current IOS ILEAK D0ญD11 = logic 1, VREF = 1.000V, measured at VOUT D0ญD11 = logic 0, VREF = 0V, measured at VOUT 90% to 10%, TA = +25ฐC 10% to 90%, TA = +25ฐC Major carry, TA = +25ฐC ฑ0.1% FS ฑ0.024% FS, 1LSB change fOUT = 5MHz, fCLK = 50MHz fOUT = 10MHz, fCLK = 50MHz fOUT = 20MHz, fCLK = 100MHz fOUT = 30MHz, fCLK = 100MHz fOUT = 30MHz, fCLK = 200MHz fOUT = 40MHz, fCLK = 200MHz fOUT = 40MHz, fCLK = 250MHz fOUT = 50MHz, fCLK = 250MHz fOUT = 40MHz, fCLK = 300MHz fOUT = 50MHz, fCLK = 300MHz Bits 0ญ11 high, TA = +25ฐC DLE1 DLE2 ILE1 ILE2 GE VREF = 1.000V, current out, into virtual ground, end-point linearity VREF = 1.000V, current out, into virtual ground, end-point linearity VOUT VOUT VOUT VOUT -0.012 -0.05 -0.012 -0.05 -1.0 ฑ0.003 ฑ0.01 ฑ0.006 ฑ0.01 ฑ0.2 Guaranteed 40 3 100 50 ตA ตA 0.012 0.05 0.012 0.05 +1.0 % FS % FS % FS SYMBOL CONDITIONS MIN TYP MAX UNITS
VREF = 1.000V, voltage out, VOUT/VIN (Note 3)
TIME-DOMAIN PERFORMANCE (Note 4) Fall Time tFALL Rise Time tRISE Glitch Energy Settling Time DYNAMIC PERFORMANCE (Notes 4, 5)
410 570 5.6 4 15 72 68 63 58 57 54 53 51 54 51 10.6
ps ps pVs ns
Spurious-Free Dynamic Range
SFDR
dBc
Output Noise
nV Hz
2
_______________________________________________________________________________________
300Msps, 12-Bit DAC with Complementary Voltage Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVEE = DVEE = -5.2V, VREF = 1.000V, TMIN to TMAX = 0ฐC to +70ฐC, unless otherwise noted.) (Note 2.) PARAMETER DIGITAL INPUTS Input Current, Logic High Input Current, Logic Low Logic "1" Voltage Logic "0" Voltage DIGITAL TIMING Data Update Rate Data-to-Clock Setup Time Data-to-Clock Hold Time Clock-to-VOUT Propagation Delay LSBs Data-to-VOUT Propagation Delay MSBs Data-to-VOUT Propagation Delay MSBs Decode Delay CONTROL AMPLIFIER Amplifier Input Resistance Multiplying Input Bandwidth Open-Loop Gain Input Offset Voltage OUTPUT PERFORMANCE Full-Scale Output Current Output Resistance Output Capacitance POWER SUPPLIES Analog Power-Supply Current Digital Power-Supply Current Power Dissipation Package Thermal Resistance, Junction to Ambient fD tSU t HOLD tPD3 tPD2 tPD1 tDD RIN BW AVOL VOS IOUT ROUT COUT AIEE DIEE PDISS TJA Minimum data rate = DC (Note 6) Bypass = 0, clocked mode (Notes 4, 7) Bypass = 0, clocked mode (Notes 4, 7) Bypass = 0, clocked mode (Notes 4, 7) Bypass = 1, transparent mode (Notes 4, 7) Bypass = 1, transparent mode (Notes 4, 7) Bypass = 1, transparent mode (Notes 4, 7) VREF = 1.000V -3dB TA = +25ฐC TA = +25ฐC VREF = 1.000V, RL = 0 VOUT, VOUT VOUT, VOUT AVEE = DVEE = -5.2V AVEE = DVEE = -5.2V 30 110 775 3 -250 19.0 49.5 300 1 0.8 2.8 2 2.9 900 800 10 20 0 20.0 50.0 15 46 150 0.98 25 60 190 1.3 825 MHz ns ns ns ns ns ps MHz kV/V ตV mA pF mA mA W ฐC/W IIH IIL VIH VIL VIH = -0.75V VIL = -1.95V -1.1 -2.0 10 1 -0.75 -1.95 200 2 0 -1.48 ตA ตA V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX555
+250 21.0 50.5
Note 2: All devices are 100% production tested at +25ฐC and are guaranteed by design for TA = TMIN to TMAX as specified. Note 3: The gain-error method of calculation is shown below: Definition: [VMEASURE(FS) - VIDEAL(FS)] x 100 GE(%) = ญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญ VIDEAL(FS) where FS indicates full-scale measurements. GE Method: GE(%) = [(4096 / 4095) VMEASURE - 16(VREF / RIN) (ROUT)] x 100 ญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญ---- 16(VREF / RIN) (ROUT) = [(4096 / 4095) VMEASURE - 1] x 100 ญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญญ 1 where: VREF = 1.000V, RIN = 800, ROUT = 50, VMEASURE = VOUT (FS).
Note 4: Dynamic and timing specifications are obtained from device characterization and simulation testing and are not production tested. Note 5: Spurious-free dynamic range is measured from the fundamental frequency to any harmonic or nonharmonic spurs within the bandwidth fCLK/2, unless otherwise specified. Note 6: Guaranteed by design. Note 7: Timing definitions are detailed in Figure 2. _______________________________________________________________________________________ 3
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