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Part: IXDP631
Category:
Discrete
-> Transistors
-> Power Management IC
Description:
Company: IXYS Corporation
Datasheet: Download IXDP631 datasheet File size : 373 kB
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Datasheet text preview:
Inverter Interface and Digital Deadtime Generator for 3-Phase PWM Controls
Type IXDP630 PI IXDP631 PI Package 18-Pin Plastic DIP 18-Pin Plastic DIP Configuration RC Oscillator Crystal Oscillator Temp. Range -40°C to +85°C -40°C to +85°C
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Features
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5 V HCMOS logic implementation maintains low power at high speed Schmitt trigger inputs and CMOS logic levels improve noise immunity Simultaneously injects equal deadtime in up to three output phases Replaces 10-12 standard SSI/MSI logic devices Allows a wide range of PWM modulation strategies Directly drives high speed optocouplers
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This 5 V HCMOS integrated circuit is intended primarily for application in three-phase, sinusoidally commutated brushless motor, induction motor, AC servomotor or UPS PWM modulator control systems. It injects the required deadtime to convert a single phase leg PWM command into the two separate logic signals required to drive the upper and lower semiconductor switches in a PWM inverter. It also provides facilities for output disable and fast overcurrent and fault condition shutdown.
In the IXDP630, deadtime programming is achieved by an internal RC oscillator. In the IXDP631, programming is achieved by use of a crystal oscillator. An alternative for both the IXDP630/ 631 is with an external clock signal. Because of its flexibility, the IXDP630/ 631 is easily utilized in a variety of brushed DC, trapezoidally commutated brushless DC, hybrid and variable reluctance step and other more exotic PWM motor drive power and control circuit designs.
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Applications
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1- and 3- Phase Motion Controls 1- and 3- Phase UPS Systems General Power Conversion Circuits Pulse Timing and Waveform Generation General Purpose Delay and Filter General Purpose Three Channel "One Shot"
Block Diagram IXDP 630/IXDP 631
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IXYS reserves the right to change limits, test conditions and dimensions.
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© 1998 IXYS All rights reserved
IXDP630 IXDP631
Symbol VCC VIN II N V0 I0 Tstg TL Definition Supply Voltage DC Input Voltage DC Input Current DC Output Voltage DC Output Current Storage Temperature Lead Soldering (max. 10 s) min. -0.5 -0.5 -1 0.5 -25 -55 Maximum Ratings max. 7 VCC + 0.5 1 VCC + 0.5 25 150 300 V V mA V mA °C °C Dimensions in inch (1" = 25.4 mm) 16-Pin Plastic DIP
Recommended Operating Conditions VCC TJ l0 fOSC Supply Voltage Operating Temperature Output Current Oscillator Frequency 4.5 -40 -8 0.001 5.5 85 8 16/24 V °C mA MHz
Symbol Vt+ VtVHYS Ii n Cin Voh Vol ICC ICCQ ICCQ
Definition/Condition Input Hi Threshold Input Lo Threshold Hysteresis Input Leakage Current Input Capacitance Output High Voltage lo = -8 mA Output Low Voltage lo = 8 mA Supply Current Outputs Unloaded Quiescent Current Outputs Unloaded IXDP630 Quiescent Current Outputs Unloaded IXDP631
min. 3.6
Characteristic Values typ. max. 2.7 1.6 1.1 5 0.8 10 10 0.4 5 0.4 1 1 10 V V V µA pF V V mA mA µA tSC 0.047 10 1 1000 0.001 - 16 5 -400 nF k MHz tSX
-10 2.4
DP630 Oscillator Section COSC ROSC fOSC Capacitor (RCIN to GND) Resistor (OSCOUT to RCIN) Frequency Range Initial Tolerance (fOSC 1MHz) Temperature Coefficient DP631 Oscillator Section fOSC VINH VINL Frequency Range Oscillator Thresholds (IXTLIN) 0.1-24 3.9 0.8 MHz V V
th o l d
% ppm/°C
tp d r o
External Oscillator fI N t t th o l d tp d r o tp d e o
SX SC
Frequency Range (ODCOUT open) Set Up Time DATA-to-XTLIN 14 Set Up Time DATA-to-OSCIN 22 Hold Time CLOCK-Data 0 Propagation Delay RESET-to-OUTPUT Propagation Delay ENABLE-to-OUTPUT
0-24
MHz nS ns ns ns ns tp d e o
15 8
20 16
© 1998 IXYS All rights reserved
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IXDP630 IXDP631
Pin Description IXDP630
Sym. Pin Description R S T 1 R, S and T are the three single3 phase inputs. Each input is 5 expanded into two outputs to generate non-overlapping drive signals, RU/RL, SU/SL, and TU/ TL. The delay from the falling edge of one line to the rising edge of the other is a function of the clock. Sym. Pin Description GND 9 CIRCUIT GROUND - 0 Volts
Pin Description IXDP631
ENAR 2 High logic input will enable the ENAS 4 outputs, as set by the proper ENAT 6 input phase. The ENA (R,S,T) signals control the drive output lines. A low logic input will force both controlled outputs to a low logic level OUT ENA 7 High logic level will enable all outputs to their related phase. The OUTENA simultaneously controls all outputs. Low input logic level will inhibit all outputs (low).
RCIN 10 The first node of the clock or network. For the IXDP630, the XTLIN RC input is applied to RCIN. For the IXDP 631, the crystal oscillator is applied to XTLIN. If an external clock is to be supplied to the chip it should be connected to this pin. OSC OUT 11 This is the output node of the oscillator. It is connected indirectly to the RCIN or XTLIN pins when using the internal oscillator as described in the applications information. It is not recommended for external use. 12 13 14 15 16 17 After the appropriate delay, the external drive outputs (R,S, T) U are in phase with their corresponding inputs; (R,S, T) L are the complementary outputs.
RESET 8 The RESET signal is active low. When a logic low RESET is applied, all outputs will go low. After releasing the RESET command within the generated delay, the outputs will align with the phase input level after the programmed delay internal.
TL TU SL SU RL RU VC C
18 Voltage Supply +5 V ± 10 %
Waveforms This diagram shows the normal operation of the IXDP630/631 after the RESET input is released. The DEADTIME is the 8 Clock periods between XU and XL when both XU and XL are a "0". The length of the DEADTIME is fixed at 8 times the period of CLK.
deadtime deadtime deadtime
noise deadtime Note: X = Any input, R, S or T. deadtime deadtime
The diagram shows OUTENA and ENAX asynchronously forcing the XU Output and the XL Output to the off state. OUTENA will force all three channels to the off state. ENAX (where X is one of the three channels) will only force the XU and XL Outputs of that channel to the off state. Note that because ENAX is asynchronous with respect to the internal clock and deadtime counters, when ENAX goes HI whatever state the deadtime counter was in immediately propagates to the output. This figure also shows that noise at the XIN input will be filtered before the XU Output or XL Output will become active, which may extend the deadtime. © 1998 IXYS All rights reserved
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