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Part: IS71V08F32GST08
Category:
Memory
-> Multi Chip Memory
-> Flash + SRAM
Description:
Company: Integrated Silicon Solution
Datasheet: Download IS71V08F32GST08 datasheet File size : 118 kB
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Datasheet text preview:
IS71V08F32GSx08 IS71V16F32GSx08
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip Package (MCP) -- 32 Mbit Simultaneous Operation Flash Memory and 8 Mbit Static RAM MCP FEATURES
· Power supply voltage 2.7V to 3.1V · High performance:
Flash: 70ns maximum access time SRAM: 70ns maximum access time
ISSI
· Erase Algorithms: · Program Algorithms:
Automatically writes and verifies data at specified address
®
PRELIMINARY INFORMATION OCTOBER 2002
Automatically preprograms/erases the flash memory entirely, or by sector
· Package: 73-ball BGA · Operating Temperature: -40C to +85C
· Hidden ROM Region:
256 byte with a Factory-serialized secure electronic serial number (ESN), which is accessible through a command sequence
FLASH FEATURES · Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum Read Current at 5 Mhz:18 mA maximum Sleep Mode: 5 µA maximum · User Configurable Banks - Bank A : 4 Mbit (8KB x 8 and 64KB x 7) - Bank B : 12 Mbit (64KB x 24) - Bank C : 12 Mbit (64KB x 24) - Bank D : 4 Mbit (64KB x 8 ) User chooses two virtual banks from a combination of four physical banks · Simultaneous R/W Operations (dual virtual bank): Zero latency between read and write operations; Data can be programmed or erased in one bank while data is simultaneously being read from the other bank
· Data Polling and Toggle Bit:
Allow for detection of program or erase cycle completion
· Ready-Busy output (RY/BY)
Detection of program or erase cycle completion
· · · ·
Over 100,000 write/erase cycles Low supply voltage (Vccf 2.5V) inhibits writes Top or Bottom Boot WP/ACC input pin: If VIL, allows partial protection of boot sectors If VIH, allows removal of boot sector protection If Vacc, program time is improved
· Low-Power Mode:
A period of no activity causes flash to enter a low-power state
SRAM FEATURES (8 Mb density) · Power Dissipation:
Operating: 25 mA maximum Standby: 15 µA maximum
· Erase Suspend/Resume:
Suspends of erase activity to allow a read in the same bank
· Chip Selects: CE1s, CE2s · Power down feature using CE1s, or CE2s or
UBs or LBs
· Sector Erase Architecture:
8 sectors of 4K words each and 63 sectors of 32K words each in Word mode, or 8 sectors of 8K bytes each and 63 sectors of 64K bytes each in Byte mode. Any combination of sectors, or the entire flash can be simultaneously erased
· Data retention supply voltage: 1.2 to 3.1 volt · Byte data control: LBs (DQ0DQ7), UBs
(DQ8DQ15) with x16 version
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B 10/21/02
1
IS71V08F32GSx08 IS71V16F32GSx08
GENERAL DESCRIPTION
ISSI
®
The flash and SRAM MCP is a 32 Mbit Flash/8 Mbit SRAM with shared data, address, and control pins. The 32 Mbit flash is composed of 2,097,152 words of 16 bits or 4,194,304 bytes of 8 bits. The 8Mb SRAM has 524,288 words of 16 bits or 1,048,576 bytes of 8 bits. The Flash memory in Word mode (or x16 version of SRAM) is accessed with data lines DQ0DQ15. The Flash memory in Byte mode (or x8 version of SRAM) is accessed with data lines DQ0-DQ7. For the x16 version of SRAM, a single byte can be accessed using UBs or LBs, or DQ0-DQ7 or DQ8-DQ15. The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations. The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM programmer. The 32 Mbit flash/8 Mbit SRAM is offered in a 73-pin BGA package. The flash is compatible with the JEDEC Flash command set standard . The flash access time is 70ns and the SRAM access time is 70ns. The Flash architecture is composed of two virtual banks which allows simultaneous operation on each. Optimized performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. Both operations would then be operating simultaneously, with zero latency.
MCP BLOCK DIAGRAM
VCCf A0-A20 A0-A20 A-1 WP/ACC RESET CEf I/Of
GND
RY/BY 32-MBIT Flash Memory DQ0-DQ15/A-1
VCCS GND A0-A18 SA LBs UBs WE OE CE1s CE2s DQ0-DQ15
8-MBIT Static RAM
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B 10/10/02
IS71V08F32GSX08 IS71V16F32GSx08
ISSI
22 A0-A20, A-1 SA CEf CE1s CE2s OE WE WP/ACC RESET UBs LBs I/Of DQ0-DQ15 16 or 8 RY/BY
®
LOGIC SYMBOL
FLASH MEMORY BLOCK DIAGRAM
V CC GND A0-A20 Upper Bank Address Y-Decoder RY/BY A0-A20 RESET WE CE I/of WP/ACC DQ0-DQ15 A0-A20 Lower Bank Latches and Control Logic STATE CONTROL & COMMAND REGISTER Control DQ0-DQ15 A0-A20 X-Decoder DQ0-DQ15 DQ0-DQ15 Upper Bank Latches and Control Logic OE I/of
Status
A0-A20
Lower Bank Address
Y-Decoder
X-Decoder OE I/of
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B 10/10/02
3
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