Description: QUAD (Burst of 4) Synchronous SRAMs<<<>>>The 36Mb IS61QDB41M36 and<<<>>>IS61QDB42M18 are synchronous, high-performance<<<>>>CMOS static random access memory<<<>>>(SRAM) devices. These SRAMs have separate I/Os,<<<>>>eliminating the need for high-speed bus turnaround.<<<>>>The rising edge of K clock initiates the read/write<<<>>>operation, and all internal operations are self-timed.<<<>>>Refer to the Timing Reference Diagram for Truth<<<>>>Table on page 8 for a description of the basic operations<<<>>>of these QUAD (Burst of 4) SRAMs.
