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Part: IS61NP25618-133TQ
Category:
Memory
-> SRAM
-> Sync. SRAM
Description: 256K X 18 Pipeline no Wait State Bus SRAM
Company: Integrated Silicon Solution
Datasheet: Download IS61NP25618-133TQ datasheet File size : 145 kB
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Datasheet text preview:
IS61NP12832 IS61NP12836 IS61NP25618 IS61NLP12832 IS61NLP12836 IS61NLP25618
128K x 32, 128K x 36 and 256K x 18 PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
· · · · · · · · · · · · · · · · 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining for TQFP Power Down mode Common data inputs and data outputs CKE pin to enable clock and suspend operation JEDEC 100-pin TQFP and 119 PBGA packages Single +3.3V power supply (± 5%) NP Version: 3.3V I/O Supply Voltage NLP Version: 2.5V I/O Supply Voltage Industrial temperature available
ISSI
®
NOVEMBER 2002
DESCRIPTION
The 4 Meg 'NP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 131,072 words by 32 bits, 131,072 words by 36 bits and 262,144 words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -150 3.8 6.7 150 -133 4.2 7.5 133 -100 5 10 100 Units ns ns MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 11/21/02
1
IS61NP12832 IS61NP12836 IS61NP25618 IS61NLP12832 IS61NLP12836 IS61NLP25618
BLOCK DIAGRAM
ISSI
®
A [0:16] or A [0:17]
ADDRESS REGISTER
A2-A16 or A2-A17
128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY
MODE A0-A1
BURST ADDRESS COUNTER
A'0-A'1
K
DATA-IN REGISTER
CLK CKE
CONTROL LOGIC K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
K
DATA-IN REGISTER
CE CE2 CE2 ADV WE BWY X OE ZZ DQa0-DQd7 or DQa0-DQb8 DQPa-DQPd 32, 36 or 18 CONTROL REGISTER
}
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
(X=a,b,c,d or a,b)
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 11/21/02
IS61NP12832 IS61NP12836 IS61NP25618 IS61NLP12832 IS61NLP12836 IS61NLP25618
PIN CONFIGURATION
119-pin PBGA (Top View) 100-Pin TQFP
ISSI
A6 A7 CE CE2 BWd BWc BWb BWa CE2 VCC GND CLK WE CKE OE ADV NC NC A8 A9
®
1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ
2
3
4
5
6
7
A6 CE2 A7 NC DQc3 DQc4 DQc6 DQc8 VCC DQd2 DQd3 DQd5 DQd7 NC A5 NC NC
A4 A3 A2 GND GND GND BWc GND NC GND BWd GND GND GND MODE A10 NC
NC ADV VCC NC CE OE NC WE VCC CLK NC CKE A1 A0 VCC A11 NC
A8 A9 A12 GND GND GND BWb GND NC GND BWa GND GND GND VCC A14 NC
A16 CE2 A15 NC DQb6 DQb5 DQb4 DQb2 VCC DQa7 DQa5 DQa4 DQa3 NC A13 NC NC
VCCQ NC NC DQb8 DQb7 VCCQ DQb3 DQb1 VCCQ DQa8 DQa6 VCCQ DQa2 DQa1 NC ZZ VCCQ
NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 VCC VCC VCC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND VCC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC
128K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable CE, CE2, CE2 Synchronous Chip Enable OE DQa-DQd MODE VCC GND VCCQ ZZ Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable
A2-A16 CLK ADV BWa-BWd WE CKE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 11/21/02
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
3
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