Description: DDR-II (Burst of 4) CIO Synchronous SRAMs<<<>>>The 36Mb IS61DDB41M36 and IS61DDB42M18<<<>>>are synchronous, high-performance CMOS static<<<>>>random access memory (SRAM) devices. These<<<>>>SRAMs have a common I/O bus. The rising edge of<<<>>>K clock initiates the read/write operation, and all<<<>>>internal operations are self-timed. Refer to the<<<>>>Timing Reference Diagram for Truth Table on p.8<<<>>>for a description of the basic operations of these<<<>>>DDR-II (Burst of 4) CIO SRAMs.
