Description: 256-MBIT DDR SDRAM<<<>>>ISSI’s 256-Mbit DDR SDRAM achieves high-speed data<<<>>>transfer using pipeline architecture and two data word<<<>>>accesses per clock cycle. The 268,435,456-bit memory<<<>>>array is internally organized as four banks of 64M-bit to<<<>>>allow concurrent operations. The pipeline allows Read<<<>>>and Write burst accesses to be virtually continuous, with<<<>>>the option to concatenate or truncate the bursts. The<<<>>>programmable features of burst length, burst sequence<<<>>>and CAS latency enable further advantages. The device<<<>>>is available in 16-bit data word size. Input data is registered<<<>>>on the I/O pins on both edges of Data Strobe<<<>>>signal(s), while output data is referenced to both edges of<<<>>>Data Strobe and both edges of CK. Commands are<<<>>>registered on the positive edges of CK. Auto Refresh,<<<>>>Active Power Down, and Pre-charge Power Down modes<<<>>>are enabled by using clock enable (CKE) and other<<<>>>inputs in an industry-standard sequence. All input and<<<>>>output voltage levels are compatible with SSTL 2.
