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Part: IS41LV4105-60JI
Category:
Memory
-> DRAM
-> EDO/FPM DRAM
Description: 1Mx4 FP
Company: Integrated Silicon Solution
Datasheet: Download IS41LV4105-60JI datasheet File size : 134 kB
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Datasheet text preview:
IS41C4105 IS41LV4105
1Meg x 4 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
FEATURES
· · · · Fast access and cycle time TTL compatible inputs and outputs Refresh Interval: 1024 cycles/16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden · JEDEC standard pinout · Single power supply: -- 5V ± 10% (IS41C4105) -- 3.3V ± 10% (IS41LV4105) · Industrial temperature available
ISSI
DESCRIPTION
®
PRELIMINARY INFORMATION SEPTEMBER 2001
The ISSI IS41C4105 and IS41LV4105 are 1,048,576 x 4-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1024 random accesses within a single row with access cycle time as short as 12 ns per 4-bit word. These features make the IS41C4105 and the IS41LV4105 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C4105 and IS41LV4105 are available in a 20-pin, 300-mil SOJ package.
KEY TIMING PARAMETERS
Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -60 60 15 30 25 110 Unit ns ns ns ns ns
PIN CONFIGURATION 20-Pin SOJ
I/O0 I/O1 WE RAS A9
1 2 3 4 5
20 19 18 17 16
GND I/O3 I/O2 CAS OE
PIN DESCRIPTIONS
A0-A9 I/O0-I/O3 WE OE RAS CAS VCC GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection
A0 A1 A2 A3 Vcc
6 7 8 9 10
15 14 13 12 11
A8 A7 A6 A5 A4
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 09/11/01 Rev. 00A
1
IS41C4105 IS41LV4105
FUNCTIONAL BLOCK DIAGRAM
ISSI
®
OE WE CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC OE RAS
CAS
CAS
WE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
COLUMN DECODERS SENSE AMPLIFIERS
REFRESH COUNTER
DATA I/O BUFFERS
I/O0-I/O3
ROW DECODER
ADDRESS BUFFERS A0-A9
MEMORY ARRAY 1,048,576 x 4
TRUTH TABLE
Function Standby Read Write: Word (Early Write) Read-Write Hidden Refresh Read W r i t e (1) RAS-Only Refresh CBR Refresh
Notes: 1. EARLY WRITE only.
RAS H L L L LHL LHL L HL
CAS H L L L L L H L
WE X H L HL H L X X
OE X L X LH L X X X
Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X
I/O High-Z DOUT DIN DOUT, DIN DOUT DOUT High-Z High-Z
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 09/11/01
IS41C4105 IS41LV4105
FUNCTIONAL DESCRIPTION
The IS41C4105 and IS41LV4105 are CMOS DRAMs o p t i m i z e d for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 20 address bits. The first ten address bits (A0-A9) are entered as row address and latter ten address bits (A0-A9) are entered as column address. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first ten bits of row address and CAS is used to latch the latter nine bits of column address.
ISSI
Refresh Cycle
®
To retain data, 1024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory: 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
Power-On
After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 09/11/01 Rev. 00A
3
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