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Part: IZ0065
Category:
Optoelectronics
-> Drivers/Controllers
-> LCDs
-> LCD Controllers and Drivers
Description:
Company: IK Semiconductor
Datasheet: Download IZ0065 datasheet File size : 522 kB
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Datasheet text preview:
TECHNICAL DATA
IZ0065 40 Channel Segment / Common Driver For Dot Matrix LCD
The IZ0065 is a LCD driver LSI which is fabricated by low power CMOS technology. Basically this LSI consists of 20 × 2 bit bi-directional shift register, 20 × 2 bit data latch and 20 × 2 bit driver. This LSI can be used a common or segment driver.
FEATURES
· Display driving bias: static -1/5 · Power supply voltage: +5V ± 10%, +3V ± 10% · Supply voltage for display: 0 ~ -5V(VEE) · Interface
FUNCTIONS
· Dot matrix LCD driver with 40-channel output. · Selectable function to use common/segment drivers simultaneously. · Input / Output signal - output: 20 × 2 channel waveform for LCD driving - input: - Serial display data and control pulse from the controller LSI. · Bias voltage (V1-V6)
driver(cascade connection) Other IZ0065
controller IZ0066 KS0066 HD44780 SED1278
· CMOS Process · Bare chip available
ABSOLUTE MAXIMUM RATING (Ta = 25oC)
Characteristic Operating Voltage Driver Supply Voltage Input Voltage 1 Input Voltage 2 (V1-V6) Operating Temperature Storage Temperature Symbol VDD VLCD VIN1 VIN2 TOPR TSTG Value -0.3 ~ 7.0 VDD - 13.5 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 VDD + 0.3 ~ VEE - 0.3 -30 ~ +85 -55 ~ +125 Unit V V V V
o o
C C
Voltage greater than above may damage to then circuit. VEE: connect protection resistor (220 ± 5%)
IN T E G R A L
1
IZ0065
ELECTRICAL CHARACTERISTICS DC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic Operating Current * Supply Current * Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Voltage Descending Symbol I DD I EE VIH VIL ILKG V OH VOL VD1 V D2 Leakage Current IV VIN =0-VDD IOH = -0.4mA IOL = +0.4mA ION=0.1mA for one of SC1-SC40 ION=0.5mA for each SC1-SC40 VIH= VDD~ VEE (Output SC1SC40:floating) * VDD-VEE=4V Test Condition fCL2=400KHz fCL1=1KHz Min 0 . 7 V DD 0 -5 V DD 0.4 -10 M ax 1 10 V DD 0 . 3 V DD 5 0 .4 1 .1 1 .5 10 µA V1-V6 V V(V1-V6), SC(SC1-SC40) µA Unit mA µA V CL1, CL2, DL1, DL2, DR1, DR2, SHL1, SHL2, M, FCS DL1, DL2, DR1, DR2 Applicable pin -
AC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic Data Shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time Clock Rise/Fall Time Data Set-up Time Data Hold Time Data Delay Time Symbol fCL tWCKH tWCKL tLS tLS tR/tF tSU tDH tD Test Condition from CL2 to CL1 from CL1 to CL2 CL=15pF Min 800 800 500 500 300 300 M ax 400 200 500 DL1, DL2, DR1, DR2, FLM DL1, DL2, DR1, DR2 ns CL1, CL2 Unit KHz Applicable pin CL2 CL1, CL2 CL2
Input/Output current excluded; When input is at the intermediate level with CMOS, excessive current flows through the input circuit to the power supply,To avoid this, input level must be fixed at «H» or «L».
IN T E G R A L
2
IZ0065
BLOCK DIAGRAM
SS CC 12
S C 1 9
S C 2 0
S C 2 1
S C 2 2
S C 3 9
S C 4 0
P ART 1 V1 V2 V3 V4 V2 LCD DRIVER V1
P ART 2
LCD DRIVER V5 V6
D ATA LATCH (20 bit)
D ATA LATCH (20 bit)
VD D Vss VEE
BID IRECTIO N AL S H IFT REGISTER (20bit)
BID IRECTIO N AL S H IFT REGISTER (20bit)
M CL1 CL2
SW
CO N TR LO GIC
F C S
D L 1
S H L 1
D R 1
D L 2
S H L 2
D R 2
IN T E G R A L
3
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