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Part: ISL6556B
Category:
Power Management
-> Desktop
Description: Optimized Multi-phase PWM Controller With Adjustable Voltage Offset
Company: Intersil Corporation
Datasheet: Download ISL6556B datasheet File size : 476 kB
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Datasheet text preview:
®
ISL6556B
D a ta Sheet M ar c h 2003 FN9097.1
Optimized Multi-Phase PWM Controller with 6-Bit DAC and Programmable Internal Temperature Compensation for VR10.X Application
The ISL6556B controls microprocessor core voltage regulation by driving up to 4 synchronous-rectified buck channels in parallel. Multi-phase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents. The ISL6556B utilizes rDS(ON) current sensing in each phase for adaptive voltage positioning (droop), channelcurrent balancing, and over-current protection. To ensure the accuracy of droop, a programmable internal temperature compensation function is implemented to nullify the effect of rDS(on) temperature sensitivity. A unity gain, differential amplifier is provided for remote voltage sensing. Any potential difference between remote and local grounds can be eliminated using the remote-sense amplifier. The precision threshold-sensitive enable input is available to accurately coordinate the start up of the ISL6556B with Intersil MOSFET driver IC. Dynamic-VIDTM technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting. The ISL6556B uses 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor.
Features
· Precision Multi-Phase Core Voltage Regulation - Differential Remote Voltage Sensing - ±0.5% System Accuracy Over Temperature and Life - Adjustable Reference-Voltage Offset · Precision rDS(on) Current Sensing - Integrated Programmable Temperature Compensation - Accurate Load-Line Programming - Accurate Channel-Current Balancing - Low-Cost, Lossless Current Sensing · Internal Shunt Regulator for 5V or 12V Biasing · Microprocessor Voltage Identification Input - Dynamic VIDTM Technology - 6-Bit VID Input - 0.8375V to 1.600V in 12.5mV Steps · Threshold Enable Function for Precision Sequencing · Over Current Protection · Over-Voltage Protection - No Additional External Components Needed - OVP Pin to drive opitional Crowbar Device · 2, 3, or 4 Phase Operation up to 1.5MHz per Phase · QFN Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile
Ordering Information
PART NUMBER ISL65 56BCB ISL65 56BCR TEMP. (oC) 0 to 105 0 to 105 PACKA GE 28-PIN SOIC 32-PIN QFN PKG. NO. M2 8.3 L 32.5X5B
Pinouts
32-LEAD QFN TOP VIEW
PGOOD ENLL GND VID4 VCC OVP
28-PIN SOIC TOP VIEW
OVP PGOOD VID4
24 PWM4
1 2 3 4 5 6 7 8 9
28 27 26 25 24 23 22 21 20 19 18 17 16 15
FS EN VCC PWM4 ISEN4 ISEN2 PWM2 PWM1 ISEN1 ISEN3 PWM3 GND RGND VSEN
31
30
29
32
28
27
26
EN
FS
VID3 VID2 VID1 VID0 VID12.5 OFS TCOMP REF
1 2 3 4 5 6 7 8 FB 10 COMP 11 PWM3 16 VSEN 13 VDIFF 12 RGND 14 GND 15 9
25
VID3 VID2 VID1 VID0 VID12.5 OFS
23 ISEN4 22 ISEN2 21 PWM2 20 PWM1 19 18 ISEN1 GND
TCOMP 10 REF 11 FB 12 COMP 13 VDIFF 14
17 ISEN3
OFSOUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Dynamic VIDTM is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
ISL6556B ISL6565BCB Block Diagram
VDIFF PGOOD OVP VCC
RGND x1 VSEN
S
OVP LATCH Q
R
POWER-ON RESET (POR)
1.24V EN
TRI-STATE OVP SOFT START AND FAULT LOGIC CLOCK AND SAWTOOTH GENERATOR FS
+200mV
PWM
PWM1
OFS
O FFSET
PWM
PWM2
REF
PWM
PWM3
VID4 VID3 VID2 VID1 VID0 VID12.5 COMP FB OC I_TRIP DYNAMIC VID D/A E/A
PWM
PWM4
CHANNEL CURRENT BALANCE
CH ANNEL DETECT
ISEN1
I_TOT
C HANNEL SAMPLE & HOLD CURRENT SENSE
ISEN2 ISEN3 ISEN4
TCO M P
T
GND
2
ISL6556B ISL6565BCR Block Diagram
VDIFF PGOOD OVP VCC ENLL
RGND x1 VSEN
S
OVP LATCH Q
R
POWER-ON RESET (POR)
1.24V EN
TRI-STATE OVP SOFT START AND FAULT LOGIC CLOCK AND SAWTOOTH GENERATOR FS
+200mV
PWM
PWM1
OFS
O FFSET
PWM
PWM2
OFSOUT REF
PWM
PWM3
VID4 VID3 VID2 VID1 VID0 VID12.5 COMP FB OC I_TRIP DYNAMIC VID D/A E/A
PWM
PWM4
CHANNEL CURRENT BALANCE
CH ANNEL DETECT
ISEN1
I_TOT
C HANNEL SAMPLE & HOLD CURRENT SENSE
ISEN2 ISEN3 ISEN4
TCO M P
T
GND
3
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