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Part: ISL6556ACR-T
Category:
Power Management
-> Desktop
Description: 3-in-1 Acpi Regulator/controller For Dual Channel DDR And DDR2 Memory Systems
Company: Intersil Corporation
Datasheet: Download ISL6556ACR-T datasheet File size : 476 kB
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Datasheet text preview:
®
ISL6556A
D a t a Sheet M a r c h 2003 FN9096.1
Optimized Multi-Phase PWM Controller with 6-Bit DAC for VR10.X Application
The ISL6556A controls microprocessor core voltage regulation by driving up to 4 synchronous-rectified buck channels in parallel. Multi-phase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents. Lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area. The ISL6556A utilizes r DS(ON) current sensing in each phase for adaptive voltage positioning (droop), channelcurrent balancing, and over-current protection. To ensure droop accuracy, an external NTC compensation circuit can be used to completely nullify the effect of temperature related variation in rDS(ON) . A unity gain, differential amplifier is provided for remote voltage sensing. Any potential difference between remote and local grounds can be eliminated using the remote-sense amplifier. The precision threshold-sensitive enable input is available to accurately coordinate the start up of the ISL6556A with Intersil MOSFET driver IC. Dynamic-VIDTM technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting. The ISL6556A uses 5V bias and has a built-in shunt regulator to allow 12V bias using only a small external limiting resistor.
Features
· Precision Multi-Phase Core Voltage Regulation - Differential Remote Voltage Sensing - ±0.5% System Accuracy Over Temperature and Life - Adjustable Reference-Voltage Offset · Precision rDS(on) Current Sensing - Accurate Load-Line Programming - Accurate Channel-Current Balancing - Low-Cost, Lossless Current Sensing · Internal Shunt Regulator for 5V or 12V Biasing · Microprocessor Voltage Identification Input - Dynamic VIDTM Technology - 6-Bit VID Input - 0.8375V to 1.600V in 12.5mV Steps · Threshold Enable Function for Precision Sequencing · Over Current Protection · Over-Voltage Protection - No Additional External Components Needed - OVP Pin to drive optional Crowbar Device · 2, 3, or 4 Phase Operation up to 1.5MHz per Phase · QFN Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile
Ordering Information
PART NUMBER ISL6556ACB ISL6556ACR TEMP. (oC) 0 to 105 0 to 105 PACKAGE 28-PIN SOIC 32-PIN QFN PKG. NO. M28.3 L32.5X5B
Pinouts
32-LEAD QFN TOP VIEW
31 PGOOD 27 ENLL 32 VID4 28 GND 25 VCC 30 OVP OVP PGOOD VID4 24 PWM4 23 ISEN4 22 ISEN2 21 PWM2 20 PWM1 19 18 ISEN1 GND VID3 VID2 VID1 VID0 VID12.5 OFS DAC 26 EN 1 2 3 4 5 6 7 8 9 10 29 FS
28-PIN SOIC TOP VIEW
28 27 26 25 24 23 22 21 20 19 18 17 16 15 FS EN VCC PWM4 ISEN4 ISEN2 PWM2 PWM1 ISEN1 ISEN3 PWM3 GND RGND VSEN
VID3 VID2 VID1 VID0 VID12.5 OFS DAC REF
1 2 3 4 5 6 7 8 COMP 11 FB 10 VSEN 13 OFSOUT 9 PWM3 16 VDIFF 12 RGND 14 GND 15
17 ISEN3
REF 1 1 FB 1 2 COMP VDIFF 13 14
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Dynamic VIDTM is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
ISL6556A ISL6565ACB Block Diagram
V D I F F PGOOD OVP VCC
RGND x1 VSEN
S
OVP LATCH Q
R
POWER-ON RESET (POR)
1.24V EN
TRI-STATE OVP SOFT START AND FAULT LOGIC CLOCK AND SAWTOOTH GENERATOR FS
+200mV
PWM
PWM1
OFS
OFFSET
PWM
PWM2
REF DAC
PWM
PWM3
VID4 VID3 VID2 VID1 VID0 VID12.5 COMP FB OC I_TRIP DYNAMIC VID D/A E/A
PWM
PWM4
CHANNEL CURRENT BALANCE
CHANNEL DETECT
ISEN1
I_TOT
CHANNEL SAMPLE & HOLD CURRENT SENSE
ISEN2 ISEN3 ISEN4
GND
2
ISL6556A ISL6565ACR Block Diagram
V D I F F PGOOD OVP VCC ENLL
RGND x1 VSEN
S
OVP LATCH Q
R
POWER-ON RESET (POR)
1.24V EN
TRI-STATE OVP SOFT START AND FAULT LOGIC CLOCK AND SAWTOOTH GENERATOR FS
+200mV
PWM
PWM1
OFS
OFFSET
PWM
PWM2
OFSOUT REF DAC
PWM
PWM3
VID4 VID3 VID2 VID1 VID0 VID12.5 COMP FB OC I_TRIP DYNAMIC VID D/A + E/A
PWM
PWM4
CHANNEL CURRENT BALANCE
CHANNEL DETECT
ISEN1 CHANNEL SAMPLE & HOLD CURRENT SENSE ISEN3 ISEN4 ISEN2
I_TOT
GND
3
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