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Part: ISL5416EVAL1
Category:
Communication
-> Wireless
-> Commlink
Description: Four-channel Wideband Programmable Downconverter
Company: Intersil Corporation
Datasheet: Download ISL5416EVAL1 datasheet File size : 416 kB
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Datasheet text preview:
®
ISL5416
D a ta Sheet F e br u a r y 2003 FN6006.2
Four-Channel Wideband Programmable DownConverter
The ISL5416 Four-Channel Wideband Programmable Digital DownConverter (WPDC) is designed for high dynamic range applications such as cellular basestations where the processing of multiple channels is required in a small physical space. The WPDC combines four channels in a single package, each including: an NCO, a digital mixer, digital filters, an AGC and a resampling filter. All channels are independently programmable and may be updated in real time. Each of the four channels can select any of the four digital input buses. Each of the tuners can process a W-CDMA channel. Channels may be cascaded or polyphased for increased bandwidth. Selectable outputs include I samples, Q samples, and AGC gain. Outputs from the part are available over the parallel, serial or uP interfaces.
Features
· Up to 95MSPS Input · Four Parallel 16-bit Fixed or 17-bit Floating Point Inputs · Programmable RF Attenuator/VGA Control · 32-Bit Programmable Carrier NCO with > 110dB SFDR · 20-bit Internal Data Path · Filter Functions - Multi-Stage Cascaded-Integrator-Comb (CIC) Filter - Two programmable FIR Filters (first up to 32-taps, second up to 64-taps) - Half Band Interpolation Filter - Resampling FIR Filter · Overall decimation from 1 to >4096 · Digital AGC with up to 96dB of Gain Range · Up to Four Independent 16-bit Parallel Outputs · Serial Output Option
Ordering Information
PA RT NUMBER ISL5416KI ISL5416EVAL1 TEMP RANGE (oC) -40 to 85 25 PACKAGE 256 BGA PKG. NO V256.17x17
· 16-bit Parallel µP Interface · 1.8V core, 3.3V I/O Operation · Evaluation Board and Configuration Software available
EVALUATION KIT
Applications
· Basestation Receivers: GSM/EDGE, CDMA2000, UMTS.
Block Diagram
TEST REGISTER O U TP U T RANGE CONTROL AOUT(15:8) INPUT CHANNEL ROUTING NCO MIXER CIC Q I I FI R1 FILTER Q FI R2 FILTER I AGC Q Q I IHBF Q I RESAMPLER Q I OUTPUT ROUTING & FORMATTING AOUT(7:0) FSYNCA OEA
AIN(16:0) ENIA CLKA
INPUT SELECT CLOC K & FORMAT
INPUT A INPUT B INPUT C INPUT D
C HANNEL O C HANNEL 1 C HANNEL 2 C HANNEL 3
CLKO1 CLKO2 /INTRPT
EOUT(15:0)
RF ATTENUATOR VGA CONTROL
JTAG
SYNCHRONIZATION SYNCO SYNCIN1 SYNCIN2
µP INTERFACE ADD(2:0) uP MODE
CE
RD or RD/WR
RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
P(15:0)
WR or DSTRB
TYPICAL CHANNEL
x1, 2, 4, 8 ROUND SATURATE
NCO
32-BIT CONTROL >110 db SFDR
x1, 2, 4, 8 ROUND SATURATE
CHANNEL 0 INPUT A AIN(16:0) ENIA CLKA INPUT FORMAT RANGE CONTROL TEST REGISTER MUX CASCADE IN DIGITAL TUNER OUTPUT FORMAT SLOT CONTROL CH 0, 1 MUXING AOUT(15:0) FSYNCA OEA
EXT AGC CNTRL CASCADE OUT INPUT B BIN(16:0) ENIB CLKB INPUT FORMAT RANGE CONTROL CHANNEL 1 AGC GAIN BOUT(15:0) OUTPUT MULTIPLEXING MUX DIGITAL TUNER OUTPUT FORMAT SLOT CONTROL CH 0, 1 MUXING FSYNCB OEB MUX
0 - 96 dB BYPASS
AIN(16:0) BIN(16:0) CIN(16:0) DIN(16:0) TEST INPUT
DIGITAL 24 16 TUNING / / MIXER 24 /
CIC 24 FILTER / 24 /
24 / GAIN 24 /
20 / FIR 20 1 /
24 / 24 /
20 GAIN / FIR 20 2 /
24 / 24 /
AGC
24 / 24 /
R O 16 / U 16 N/ D
F I F O
16 16 / IHBF / RESAMPLING 16 16 FILTER / /
16 / 16 /
MUX
MUX
1-5 STAGES R=2-64K BYPASS
1-32 TAPS R=1-8 BYPASS
1-64 TAPS R=1-8 BYPASS
SELECT FORMAT
CASCADE INPUTS
FILTER CASCADE OUTPUT
24 / / 24 MUX
TO SERIAL TO PARALLEL TO uP SEQUENCING INTERFACE ROUTING AND ROUTING
MUX
M UX
2
CIN(16:0) ENIC CLKC DIN(16:0) ENID CLKD EOUT(15:0) RESET
ISL5416
CHANNEL 2 INPUT C INPUT FORMAT RANGE CONTROL
COUT(15:0) FSYNCC OEC
DIGITAL TUNER
OUTPUT FORMAT
SLOT CONTROL CH 2, 3 MUXING
INPUT D INPUT FORMAT RANGE CONTROL
CHANNEL 3 AGC GAIN DOUT(15:0) DIGITAL TUNER OUTPUT FORMAT FSYNCD SLOT CONTROL CH 2, 3 MUXING SERIAL OUTPUTS SEQUENCED uP READ DATA JTAG SYNCHRONIZATION uP INTERFACE P(15:0), uPMODE, RD (RD/WR), WR (DSTRB), CE, ADD(2:0) SYNCO SYNCIN1 SYNCIN2 OED CLKO1 CLKO2/ INTRPT
MUX
TRST TMS TCLK TDI TDO
ISL5416
256-LEAD BGA TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A Ain9 B Ain8 C Ain7 D Ain6 E Ain5 F Ain3 G Ain2 H Ain0 J CLKC K GND L Cin14 M Cin12 N Cin10 P Cin9 R GND T Din8 Din 7 Din5 ENIC Cin2 CE Eout0 Cout0 Cout2 O EC C out4 VccIO FSYNCD Dout8 Cout9 Din9 Vcc Din6 ENID Din2 Din1 Eout1 Dout1 Dout2 V cc Dout5 Dout6 Dout7 Dout9 GND Cin11 Din10 Din11 Din4 Din3 Vcc Din0 Dout0 P1 OED Dout4 GND VccIO Dout10 Cout10 Cin13 Din12 D in13 GND G ND WR RD Vcc P0 Dout3 Add0 Dout11 Dout12 Cout12 Cout11 Cin15 Eout3 Din15 Din14 TRST Add2 G ND A dd1 G ND P2 Vcc Cin16 Din16 Eout4 Eout5 E out2 P3 P4 Dout15 CLKO2/ CLKO1 Cout15 INTRP T Dout13 Dout14 Cout14 Cout13 VccIO CLKD Eout6 E out7 GND G ND P5 P6 Bout0 VccIO Aout0 Bin0 Vcc Eout8 E out9 GND P7 Bout1 Bout2 Aout1 Aout2 Ain1 Bin1 Bin2 TMS TDI P8 GND Bout3 Aout3 Vcc RESET Vcc Bin3 GND GND GND uPmode G ND P10 P9 B out5 Bout4 V ccIO Aout4 A out5 Ain4 Bin4 Bin5 Eout10 Bin13 Eout11 Vcc P13 P11 TD O GND Bout6 Bout7 Aout6 A out7 Bin6 Bin7 GND Bin14 Bin15 Eout12 Eout14 P14 P12 Bout15 Bout14 B out8 B out9 Ao ut8 A out9 Bin8 ENIB Bin11 Bin12 Ain13 Bin16 C LK B P15 VccIO O EB VccIO FSYNCB VccIO Bout10 Aout10 Bin9 Bin10 Vcc Vcc Ai n 1 5 Ain16 Eout15 GND SYNCIn2 OEA Vcc Bout13 Bout12 Bout11 FSYNCA ENIA Ain10 Ain11 Ai n12 Ain14 Eout13 CLKA SYNCIn1 SYNCO Aout15 Aout14 Aout13 GND Aout12 Aout11
Cin8
Cin7
Cin 6
Cin5
Cin4
Cin3
Cin1
Cin0
Cout1
T CLK
Cout3
C out5
C o u t 6 FSYN CC C o u t 7
Co ut8
POWER PIN GROUND PIN
SIGNAL PIN THERMAL BALL NC (NO CONNECTION)
Vcc = +1.8V CORE SUPPLY VOLTAGE VccIO = +3.3V I/O SUPPLY VOLTAGE
NOTE: Thermal Balls should be connected to the ground plane Unused Input Balls should be connected to ground or VccIO as appropriate
3
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