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Part: ISL5314
Category:
Analog & Mixed-Signal Processing
Description: Commlinktm Direct Digital Synthesizer
Company: Intersil Corporation
Datasheet: Download ISL5314 datasheet File size : 416 kB
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TM
ISL5314
D a t a Sheet S e pt e m b er 2001 Fi l e Number 49 01. 1
Direct Digital Synthesizer
The 14-bit ISL5314 provides a complete Direct Digital Synthesizer (DDS) system in a single 48-pin LQFP package. A 48-bit Programmable Carrier NCO (numerically controlled oscillator) and a high speed 14-bit DAC (digital to analog converter) are integrated into a stand alone DDS. The DDS accepts 48-bit center and offset frequency control information via a parallel processor interface. A 40-bit frequency tuning word can also be loaded via an asynchronous serial interface. Modulation control is provided by 3 external pins. The PH0 and PH1 pins select phase offsets of 0, 90, 180 and 270 degrees, while the ENOFR pin enables or zeros the offset frequency word to the phase accumulator. The parallel processor interface has an 8-bit write-only data input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe (WR), and a Write Enable (WE). The processor can update all registers simultaneously by loading a set of master registers, then transfer all master registers to the slave registers by asserting the UPDATE pin.
Features
· 125MSPS output sample rate with 5V digital supply · 100MSPS output sample rate with 3.3V digital supply · 14-bit digital-to-analog (DAC) with internal reference · Parallel control interface for fast tuning (50MSPS control register write rate) and serial control interface · 48-bit programmable frequency control · Offset frequency register and enable pin for fast FSK · Small 48-pin LQFP packaging
Applications
· Programmable local oscillator · FSK, PSK modulation · Direct digital synthesis · Clock generation
Pinout
48- PIN LQFP (Q48.7X7A) TOP VIEW
C3 C4 C5 C6 C7 DVDD WR DG ND WE NC A0 A1 48 47 4 6 45 44 4 3 42 41 40 39 38 3 7 36 35 2 34 3 33 4 32 5 31 6 ISL5 314 30 7 29 8 28 9 27 10 26 11 25 12 13 1 4 15 1 6 17 18 19 20 21 22 2 3 24 1
Ordering Information
PA RT NUMBER IS L5314IN IS L5314EV AL2 TEMP. RANGE (o C ) -40 to 85 25 P ACKAGE 48 LQFP PKG. NO. Q48.7X7A
C2 C1 C0 ENOFR DGND CLK DV DD RESET UPDATE COMPOUT REFLO REFIO
Evaluation Board
Block Diagram
C(7:0 ) A(3:0 ) WR WE UPDATE SERIAL MODULATION CO NT RO L CONTROL SDATA SSYNC SCLK COMPOUT MASTER
PHASE ACCUM.
+
ININ+ COMP1 COMP2 IOUTA IOUTB REFIO REFLO
A2 A3 PH0 PH1 SSYNC DVDD SCLK DGND DGND SDATA DVDD DGND
ENOFR PH(1:0 )
INT REF
RESET CL K
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 CommLinkTM is a trademark of Intersil Corporation.
FSADJ COMP1 AG ND AGND IOUTB IOUTA COMP2 AVDD AG ND IN+ IN AG ND
SINE WAVE ROM
14 BIT DAC
SLAVE
ISL5314 Typical Application Circuit (Parallel Control Mode, Sinewave Generation)
SDATA, SSYNC, SCLK (IN PARALLEL CONTROL MODE, SERI AL CONTROL CAN ALSO BE USED IF DESIRED.) WRITE CLOCK (WR) WRITE ENABLE 3
µPROCESSOR/
FPGA/CPLD
A3:A0 BUS 8 C7:C0 BUS
4
CLOCK SOURCE f CLK
DVPP
0.1µF
C2 C1 C0 ENOFR DG ND CL K DV DD R ESET UPDATE COMPOUT REFLO REFIO 0 .1µF
48 47 46 45 44 43 42 4 1 40 39 38 37 36 35 2 34 3 33 4 32 5 31 6 ISL5314 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 1 7 18 1 9 20 21 22 23 24 1
C3 C4 C5 C6 C7 DV DD WR DG ND WE NC A0 A1
A2 A3 PH0 PH1 SSYNC DVDD SCLK DG ND DG ND SDATA DVDD DG ND
DV P P 0.1µF DVPP 0.1µF
F S ADJ COMP1 AG ND AG ND IOUTB IOUTA COMP2 AVDD AGN D IN+ INAGND
0.1µF RSET 2k AVPP 0.1µF
AVPP 0.1µF
50 50
(IOUTA) ANALOG OUTPUT
FERRITE BEAD + +5V POWER SOURCE 1 0µF DVPP (DIGI TAL POWER PLANE) 10µH FERRITE BEAD + 10µF 1 0µH 0. 1µF DGND AVPP (ANALOG POWER PLANE) 0.1 µF AG ND 1µF 1µF
2
ISL5314 Functional Description
The ISL5314 is an NCO with an integrated 14-bit DAC designed to run in excess of 125MSPS. The NCO is a 16-bit output design, which is rounded to fourteen bits for input to the DAC. The frequency control is the sum of a 48-bit center frequency word, a 48-bit offset frequency word, and a 40-bit serially loaded tuning word. The three components are added modulo 48 bits with the alignment shown in Table 1. Each of the three terms can be zeroed independently (via the microprocessor interface for the center and serial frequency registers and via the ENOFR pin for the offset frequency term). four address pins (A3:A0), a write strobe (WR), and a write enable (WE). The interface is a master/slave type. The processor interface loads a set of master registers. The contents of the master set of registers is then transferred to a slave set of registers by asserting a pin (UPDATE). This allows all of the bits of the frequency control to be updated simultaneously. The rate which the user writes (WR) to these registers does not have to be the same rate as the DDS clock rate (the rate of the NCO and DAC; pin CLK). It is expected that most applications will have a slower register write rate than the DDS clock rate. It takes one WR cycle at the write rate for each register that is written and another eleven CLK cycles at the DDS rate to write and obtain a new output, assuming that the UPDATE pin is always active. If the UPDATE pin is not active until after the new word has been written, it takes fourteen CLK cycles, rather than eleven. For cases which require the output to be updated with all of the new frequency information present, it is necessary that the UPDATE be inactive until after all of the new frequency word has been written to the device. See the Timing Diagrams for more information. The parallel registers can be written at a rate of CLK/2, such that updated control words can be pipelined. If the application does not require all registers to be written, then the output frequency can be changed more quickly. For example, if only 32 bits of frequency information are needed and it is desired that the output be updated all at once, then it takes four WR cycles, then the assertion low of the UPDATE pin, plus another fourteen CLK cycles at the DDS rate to write and update a new frequency. The timing is the same whether writing to the center or offset frequency registers. For faster frequency update, consider the ENOFR (Enable Offset Frequency Register) option. Once the values have been written to the center and offset frequency registers, the user can enable and disable the offset frequency register, which is added to the center frequency value when enabled. The ENOFR pin has a latency of fourteen CLK cycles, but simplifies the interface because the only pin that has to be toggled is the ENOFR pin. See the FSK explanation for more information.
Frequency Generation
The output frequency of the part is determined by the summation of three registers: fOU T = fC LK x ((CF + OF +SF) mod (248))/ (248), where CF is the center frequency register, OF is the offset frequency register, SF is the serial frequency register and fCLK is the DDS clock rate. With a 125MSPS clock rate, the center frequency can be programmed to (125 x 106)/(248) = 0.4 µHz resolution. The addition of the frequency control words can be interpreted as two's complement if convenient. For example, if the center frequency is set to 4000...00h and the offset frequency set to C000..00h, the programmed center frequency would be fCLK/4 and the programmed offset frequency -fCLK/4. The sum would be 10000..00h, but because only the lower 48 bits are retained, the effective frequency would be 0. In reality, frequencies above 8000...00h alias below fCLK/2 (the output of the part is real), so the MSB is only provided as a convenience for two's complement calculations. The frequency control of the NCO is the change in phase per clock period or d/dt. This is integrated by the phase accumulator to obtain frequency. The most significant 24 bits of phase are then mapped to 16 bits of amplitude in a sine look-up table function. The range of d/dt is 01 with 1 equaling 360 degrees or (2 x pi) per clock period. The phase accumulator output is also 01 with 1 equaling 360 degrees. The operations are modulo 48 bits because the MSB (bit 47) aligns with the most significant address bit of the sine ROM and the ROM contains one cycle of a sinusoid. The MSB is weighted at 180 degrees. Full scale is 360 degrees minus one LSB and the phase then rolls over to 0 degrees for the next cycle of the sinusoid. The DDS can be clocked with either a sinusoidal or a square wave. Refer to the digital inputs VIH and VIL values in the electrical specifications table.
Serial Interface
A serial interface is provided for loading a tuning frequency. This interface can be asynchronous to the master clock of the part. When the tuning word has been shifted into the part, it is loaded into a holding register by the serial interface clock, SCLK. This loading triggers a synchronization circuit to transfer the data to a slave register synchronous with the master clock. A minimum of eleven serial clocks (at minimum serial word size of eight) are necessary to complete the transfer to the slave register. Another twelve DDS CLK cycles are necessary before the output of the DDS reflects the new frequency. Serial loading latency = ((8 x N + 3) x SCLK)+ 12 x fC LK,
Parallel Interface
The processor interface is an 8-bit parallel write only interface. The interface consists of eight data bits (C7:C0),
3
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