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Part: ISL5239KI
Category:
Communication
-> Wireless
-> Commlink
Description: Pre-distortion Linearizer
Company: Intersil Corporation
Datasheet: Download ISL5239KI datasheet File size : 416 kB
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Datasheet text preview:
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ISL5239
D a t a Sheet J u ne 2002 F N80 39.0
Pre-Distortion Linearizer
The ISL5239 Pre-Distortion Linearizer (PDP) is a full featured component for Power Amplifier (PA) linearization to improve PA power efficiency and reduce PA cost. The Radio Frequency (RF) PA is one of the most expensive and power-consuming devices in any wireless communication system. The ideal RF PA would have an entirely linear relationship between input and output, expressed as a simple gain which applies at all power levels. Unfortunately, realizable RF amplifiers are not completely linear and the use of pre-distortion techniques allows the substitution of lower cost/power PA's for higher cost/power PA's. The ISL5239 pre-distortion linearizer enables the linearization of less expensive PA's to provide more efficient operation closer to saturation. This provides the benefit of improved linearity and efficiency, while reducing PA cost and operational expense. The ISL5239 features a 125 MHz pre-distortion bandwidth capable of full 5th order intermodulation correction for signal bandwidths up to 20 MHz. This bandwidth is particularly well suited for 3G cellular deployments of UMTS and CDMA2000. The device also corrects for PA memory effects that limit predistortion performance including self heating. The ISL5239 combines an input formatter and interpolator, pre-distortion linearizer, an IF converter, correction filter, gain/phase/offset adjustment, output formatter, and input and feedback capture memories into a single chip controlled by a 16-bit linearizer interface. The ISL5239 supports log of power, linear magnitude, and linear power based pre-distortion, utilizing two Look-Up Table (LUT) based algorithms for the pre-distortion correction. The
device provides programmable scaling and offset correction, and provides for phase imbalance adjustment.
Features
· Output Sample Rates Up to 125MSPS · Full 20 MHz Signal Bandwidth · Dynamic Memory Effects Compensation · Input and Feedback Capture Memories · LUT-based Digital Pre-distortion · Two 18-bit Output Busses with Programmable Bit-Width · 16-Bit Parallel µProcessor Interface · Input Interpolator x2, x4, x8 · Programmable Frequency Response Correction · Low Power Architecture · Threshold Comparator for Internal Triggering · Quadrature or Digital IF Architecture · Lowest-Cost Full-Featured Part Available
Applications
· Base Station Power Amplifier Linearization · Operates with ISL5217 in Software Radio Solutions · Compatible with the ISL5961 or ISL5929 D/A Converters
Ordering Information
PAR T N UMBER ISL5239KI ISL5239EVAL1 TEMP RANGE ( oC) -40 to 85 25 PAC KAGE 196 Ld BGA Evaluation Kit PKG. NO V196.15x15
Block Diagram
CL K TRIGIN IIN QIN CLKOU T ISTRB
TRIGOUT A P CS WR RD BUSY RESET
SERCLK SERSYNC SEROUT SERIN INPUT FORMATTER AND INTERPOLATOR X1, X2, X4, X8 PRE-DISTORTER WITH TWO 1K x 60 L UT s IF CONVERTER REAL 1X REAL 2X COMPLEX C ORRECTI ON FILTER REAL 1X REAL 2X COMPLEX GAIN / PHASE OFFSET ADJUST OUTPUT DATA FORMATTER 8 -1 8 BIT-WIDTH
IOUT QOUT
uP INTERFACE
INPUT MEMORY (2k x 32) FEEDB ACK MEMORY (1k x 20) F BCL K FB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved CommLinkTM is a trademark of Intersil Americas Inc.
Functional Block Diagram
ISL5239 Pre-Distortion Linearizer
IIN QI N C LKOUT ISTRB
OFFSET BIN ARY
MUX
BYPASS
BYPASS
BYPASS INPUT OR TEST
BYPASS PRE-D OR BYPASS PD I,Q IF CONV.
BYPASS CORRECTION FILTER REAL 1X REAL 2X COMPLEX
BYPASS GAIN / PHASE OFFSET ADJ UST. OUTPUT DAT A FORMATTER 8-18 BIT-WIDTH
IOUT QOUT
DE-MUX
HAL F HAL F HAL F BAND BAND BANDI / FILTER FILTER FILTER / / Q / / / 1 2 3 20 18 20 IFIP I,Q I CM TEST Q
INPUT TYPE (PAR/SERIAL)
TEST FUN C. SEL. OFFSET SCALE PD MAG. LUT DATA I
TMS TDI TCK TRST TDO
L UT ADDRESS CALCULATION ADDR DAT A L UT POWER
BYPASS
MODE
HM, KM, LM, GM, DC OFFSETS OU TPUT WORD WIDTH SEL. OUTPUT VALUE TYPE COEF. DATA REAL PIPELINE SEL. COEF. ADDR. SERIAL INPUT EN. COEF. B SELECT
2
JTAG LUT DATA Q LUT DELTA DATA I LUT DELTA DATA Q ACTIVE LUT LUT ADDR LUT ADDR AUTO INCR. PWR INTGR PER. PWR LOW PWR HIGH MECHANY EL 3 MOR N EFFECT COMPENSATION TRIGIN PD MAG. MAX MIN uP TRIG SEL IFIP I,Q PD I,Q PD MAG. INPUT SEL TRIG INPUT DELAY COUNT uP INPUT STATE FB STATE ADDR SER. OUTPUT EN. FB DELAY COUNT uP FORMAT PAR. TO SERIAL THRESHOLD COMPARE POWER INTEGRATOR COEF. A COEF. B SERIAL TO PAR. DAT A
TRIGOUT
ISL5239
SERIN SER CLK SERSYNC SEROUT
EXTERNAL MEMORY EFFECTS FPGA F BCL K FB
ADDR
DAT A
INPUT CAPTURE MEMORY 2K CM TEST I,Q MEMORY SELECT
FEEDBACK CAPTURE MEMORY 1K
CLK A P CS WR RD BUSY RESET
uP INTERFACE
ISL5239 Pinout
196 CABGA
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A NC B ISTRB C A3 D CS E P0 F VCCIO G P7 H P10 J CL K K P1 3 L DCTEST M QIN16 N TRST P NC VCCC QIN1 2 Q IN8 QI N5 QIN1 I OUT15 IOUT14 VCCIO G ND IOUT6 IOUT5 V CCC NC NC QIN14 QIN10 V CCC QIN3 I OUT17 IIOUT12 IOUT10 IOUT8 GN D VCCIO NC IO UT 1 QIN15 QIN1 3 QIN11 QIN7 QIN4 IOUT16 GND IOUT7 V CCIO IOUT3 IOUT0 IOUT2 F BCL K T DI TMS QIN1 7 QI N9 QIN 2 VCCIO I OUT13 IOUT9 V CCC IOUT4 F B1 TRIGIN F B2 T DO T CK BUS Y QI N6 QIN 0 V CCC GND IOUT11 G ND F B0 VCCC F B3 FB4 G ND RESET P14 P15 TRIGOUT F B7 FB 6 F B5 F B8 P1 2 P6 P5 GND P8 P11 P9 SEROUT F B9 FB1 2 FB11 SERIN P1 P2 P3 P4 FB13 FB16 FB15 GND FB10 VCCC RD A4 WR II N5 G ND VCCC QOUT14 QOUT10 FB14 FB19 FB18 V CCC A1 A5 IIN13 IIN10 IIN6 IIN1 QOUT17 QOUT13 QOUT8 QOUT2 A0 A2 IIN15 IIN11 IIN8 IIN2 QOUT16 QOUT12 VCCC QOUT7 QOUT1 QOUT3 QOUT0 NC IIN17 II N14 V CCC II N7 IIN3 VCCI O VCCIO QOUT9 QOUT6 QOUT4 NC G ND VCCC IIN16 IIN12 II N9 IIN4 IIN0 QOUT15 G ND QOUT11 G ND VCCIO V CCC NC
VCCIO QOUT5
FB17
VCCIO
SERSYNC GND
VCCIO SERCLK CLKOUT
POWER PIN GROUND PIN
SIGNAL PIN THERMAL BALL NC (Do not connect)
Pin Descriptions
NAME POWER SUPPLY VCCC VCCIO GN D CL K RES ET P I I I/O Positive Device Core Power Supply Voltage, 1.8V ±0.18V. Positive Device Input/Output Power Supply Voltage, 3.3V ±0.165V. Common Ground, 0V Input Clock. Rising edge drives all of the devices synchronous operations, except feedback capture. Reset. (Active Low). Asserting reset will clear all configuration registers to their default values, reset all internal states, and halt all processing. 16-bit bi-directional data bus that operates with A, CS, RD, and WR to write to and read from the devices internal control registers. When the host system asserts CS and RD simultaneously, P is an output bus, under all other conditions, it is an input bus. Bit 15 is the MSB. TY PE DESC RIPTION
MICROPROCE SSOR INTERFACE AND CONTROL
3
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