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Part: ISL5216
Category:
Communication
-> Wireless
-> Commlink
Description: ISL5216 Datasheet
Company: Intersil Corporation
Datasheet: Download ISL5216 datasheet File size : 416 kB
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ISL5216
TM
Da ta Sheet
F e b r u a r y 2002
FN6013.1
Four-Channel Programmable Digital DownConverter
The ISL5216 Quad Programmable Digital DownConverter (QPDC) is designed for high dynamic range applications such as cellular basestations where multiple channel processing is required in a small physical space. The QPDC combines into a single package a set of four channels which include: digital mixers, a quadrature carrier NCO, digital filters, a resampling filter, a Cartesian-to-polar coordinate converter and an AGC loop. The ISL5216 accepts four channels of 16-bit fixed or up to 14-bit mantissa / 3-bit exponent floating point real or complex digitized IF samples which are mixed with local quadrature sinusoids. Each channel carrier NCO frequency is set independently by the microprocessor. The output of the mixers are filtered with a CIC and FIR filters, with a variety of decimation options. Gain adjustment is provided on the filtered signal. The digital AGC provides a gain adjust range of up to 96dB with programmable thresholds and slew rates. A cartesian to polar coordinate converter provides magnitude and phase outputs. A frequency discriminator is also provided to allow FM demodulation. Selectable outputs include I samples, Q samples, Magnitude, Phase, Frequency and AGC gain. The output resolution is selectable from 4-bit fixed point to 32-bit floating point. Output bandwidths in excess of 1 MHz are achievable using a single channel. Wider bandwidths are available by cascading or polyphasing multiple channels.
Features
· Up to 95MSPS Input · Four Independently Programmable Downconverter Channels in a single package · Four Parallel 17-Bit Inputs providing 16-bit fixed or one of several 17-bit floating point formats · 32-Bit Programmable Carrier NCO with > 115dB SFDR · 110dB FIR Out of Band Attenuation · Decimation from 4 to >65536 · 24-bit Internal Data Path · Digital AGC with up to 96dB of Gain Range · Filter Functions - 1- to 5-Stage CIC Filter - Halfband Decimation and Interpolation FIR Filtering - Programmable FIR Filtering - Resampling FIR Filtering · Cascadable Filtering for Additional Bandwidth · Four Independent Serial Outputs · 2.5V Core, 3.3V I/O Operation
Applications
· Narrow-Band TDMA through IS-95 CDMA Digital Software Radio and Basestation Receivers · Wide-Band Applications: W-CDMA and UMTS Digital Software Radio and Basestation Receivers
Ordering Information
PART NUMBER ISL5216KI ISL5216KI-1 TEMP RANGE (oC) -40 to 85 -40 to 85 PACKAGE PKG. NO
196 d 0.8 mm V196.12x12 BGA 196 d 1.0 mm V196.15x15 BGA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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ISL5216 Block Diagram
µP TEST REGISTER
INPUT SELECT, FORMAT, DEMUX
LEVEL DETECTOR
SCLK A(15:-1) ENIA I NCO / MIXER / CIC Q CHANNEL 0 FIR FILTERS, AGC, CARTESIAN-TO-POLAR COORDINATE CONVERTER SYNCA SD1A SD2A
INPUT SELECT, FORMAT, DEMUX
B(15:-1) ENIB INPUT SELECT, FORMAT, DEMUX I NCO / MIXER / CIC Q CHANNEL 1 C(15:-1) ENIC INPUT SELECT, FORMAT, DEMUX D(15:-1) CHANNEL 2 ENID I NCO / MIXER / CIC Q BUS ROUTING FIR FILTERS, AGC, CARTESIAN-TO-POLAR COORDINATE CONVERTER OUTPUT SELECT, FORMAT, SERIALIZE SYNCC SD1C SD2C FIR FILTERS, AGC, CARTESIAN-TO-POLAR COORDINATE CONVERTER SYNCB SD1B SD2B
INPUT SELECT, FORMAT, DEMUX
I NCO / MIXER / CIC Q CHANNEL 3
FIR FILTERS, AGC, CARTESIAN-TO-POLAR COORDINATE CONVERTER
SYNCD SD1D SD2D
CLK RESET SYNCI SYNCO SYNCI0 SYNCI1 SYNCI2 SYNCI3 TRST TCLK TMS TDI TDO
INTRPT µP INTERFACE
P(15:0)
ADD(2:0)
RD or RD / WR
WR or DSTRB
µP MODE
CE
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ISL5216 Pinout
196 LEAD BGA TOP VIEW
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2
3
4
5
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7
8
9
10
11
12
13
14
A A5 B A3 C A1 D B15 E B13 F B11 G B9 H CLK J B7 K B5 L B3 M B1 N C15 P C13 C11 C9 C7 C5 C3 C1 ENIC D14 D12 D10 D8 D6 D4 C14 C10 C8 GND VCC1 GND VCC1 GND VCC2 D9 D7 D5 D2 B0 C12 C6 C4 C2 C0 D15 D13 D11 ENID D3 D1 D0 B2 ENIB TDI Cm1 Dm1 CE RD WR VCC1 B4 Bm1 µP MODE P1 GND P0 GND B6 P3 VCC1 P2 VCC2 B8 TRST SYNCI0 P5 GND P4 GND GND TCLK SYNCI1 P7 VCC1 P6 VCC1 B10 TMS SYNCI2 P9 GND P8 GND B12 P11 VCC2 P10 A0 B14 Am1 TDO SYNCI3 ADD2 RESET P13 P12 A2 A4 ENIA A12 A14 SD2A SD1B SD2B SD2C SD2D INTRPT P15 P14 A6 A8 A10 VCC1 GND VCC1 GND VCC2 GND SD1C SD1D ADD0 ADD1 A7 A9 A11 A13 A15 SD1A SYNCA SYNCB SCLK SYNCC SYNCD SYNCI SYNCO
POWER PIN GROUND PIN
SIGNAL PIN THERMAL BALL NC (NO CONNECTION)
VCC1 = +2.5V CORE SUPPLY VOLTAGE VCC2 = +3.3V I/O SUPPLY VOLTAGE
Others parts begin by is
IS-1 IS-2 IS-3 IS-4 IS-5 IS-6 IS-7 IS-8 IS-9 IS-10 IS-11 IS-12 IS-13 IS-14 IS-15 IS-16 IS-17 IS-18 IS-19 IS-20 IS-21 IS-22 IS-23 IS-24 IS-25 IS-26 IS-27 IS-28 IS-29 IS-30 IS-31 IS-32 IS-33 IS-34 IS-35 IS-36 IS-37 IS-38 IS-39 IS-40 IS-41 IS-42 IS-43 IS-44 IS-45 IS-46 IS-47 IS-48 IS-49 IS-50 IS-51 IS-52 IS-53 IS-54 IS-55 IS-56 IS-57 IS-58 IS-59 IS-60 IS-61 IS-62
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