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Part: ISL3985IR-TK
Category:
Communication
-> Wireless
-> Wireless LAN
Description: 2.4GHz Power Amplifier And Detector
Company: Intersil Corporation
Datasheet: Download ISL3985IR-TK datasheet File size : 262 kB
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Datasheet text preview:
®
ISL3985
D a ta Sheet Ju ly 2003 FN8007.1
PRELIMINARY
2.4GHz Power Amplifier and Detector
The ISL3985 is a 2.4GHz monolithic SiGe Power Amplifier designed to operate in the ISM Band. It features two low voltage single supply stages. Cascaded, they deliver 20dBm (Typ) output power for the typical DSSS signal. In addition, the device includes a 2.4GHz detector which is accurate over a 15dB dynamic range within (±)1dB. Therefore, an accurate ALC function can be implemented. The ISL3985 is housed in a 16 lead QFN package.
Features
· Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.6V · Output Power . . . . . . . . . . . 20dBm (Typ) at ACPR, DSSS, 1st Side Lobe < -30dBc, 2nd Side Lobe < -50dBc · Power Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . 25.5dB (Typ) · Detector Linear Input Power Range . . . . . . . . . . . . . .15dB · Detector Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1dB · QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile
Ordering Information
PART NUMBER ISL3985 IR ISL3985 IR-T K TEMP RANGE (oC) -40 to 85 -40 to 85 PA CKAGE 16 Ld. QFN PKG. DWG. # L16.5x5B
Applications
· Systems Targeting IEEE802.11 WLANs @ 2.4GHz · Wireless Local Area Networks (WLAN) · PCMCIA Wireless Transceivers · ISM Systems Including Automatic Level Control (ALC) · TDMA Packet Protocol Radios
Tape and Reel (1000 units)
Simplified Block Diagram
DS_VCC
Pinouts
RF_OUT
RF_IN PEAK DETECTOR
ISL3985 (QFN) TOP VIEW
12 RF_IN 11 GND 10 GND
BIAS
LOG
13
9
GND
DET_OUT VCC_DET
PE REXT DET_OUT
GND GND RF_OUT GND
14
PE BIAS_GND
15
16
1
2
3
REXT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved PRISM® is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc.
BIAS_VCC
DS_VCC
GND
4
5
6
7
8
ISL3985 Pin Descriptions
PIN NUMBER 1 2 NAME DESCRIPTION
BIAS_VCC Power Supply. REXT Bias Resistor, biasing scheme independent of absolute temperature. Driver Stage Power Supply. DC and RF Ground. RF Output of the Power Amplifier. DC and RF Ground. RF Input of the Power Amplifier. Detector Output. Detector Power Supply. Digital Input Control Pin to enable operation of the Power Amplifier. Enable logic level is high.
3 4, 5 6 7, 8, 9, 10, 11 12 13 14 15
D S_VCC GND RF_OUT GN D RF _IN DET_OUT VCC_DET PE
The ISL3985 power detect function provides a DC output voltage that is proportional to the logarithm of the output power. For an output power of 23dBm, the detector is accurate to within 0.5dB. The slope of the detector output voltage is 100mV/dB over a 15dB dynamic range. A simple application of the detector is to provide in-line monitoring of the output power using a DC voltmeter. A more value added application would use one of Intersil PRISM Baseband Processors to dynamically monitor the ISL3985 output power and to control transmit power by adjusting the AGC of the previous state to provide the best possible error free data transfer rate for any given environment. Closed loop power control is very important feature which compensates for variability in the transmit chain (radio to radio, channel to channel, over temperature...). The ISL3985 power up/down feature integrates the power down capability onto the IC and requires no external components thus freeing up board space and reducing external component count and cost. When the CMOS compatible Power Enable (PE) pin is driven low, the total supply current drops to under 50µA in, typically, 300ns. When the PE pin is driven high, the full ISL3985 output power is available in a few hundred nanoseconds. In summary, the ISL3985 RFPA provides a highly cost effective solution for the PA function by integrating many features that would require significant development time, drive up the total bill of materials cost and consume precious board space. It mates seamlessly with the other PRISM ICs to provide a highly integrated, cost effective WLAN solution in the 2.4 to 2.5GHz ISM band.
16 Exposed Pad
BIAS_GND DC and RF Ground. N/A DC and RF Ground
The ISL3985 works seamlessly with the PRISM II and PRISM 2.5 and 3 WLAN chip set components to complete a highly integrated, cost effective WLAN solution in the 2.4 to 2.5GHz ISM band. The ISL3985 is fabricated in the fastest SiGe BiCMOS process available allowing superior RF performance, normally found only in GaAs ICs. Cost effective functions, normally requiring external components, are integrated into one IC. The ISL3985 integrates the following functions in one compact 16 pin QFN: · Two Stage, 25.5dB Gain RFPA, · Logarithmic power detect function (15dB Dynamic Range), · CMOS level compatible Power Up/Down function, · Single Supply, 2.7V to 3.6V Operation. The ISL3985 contains a highly linear RFPA designed to deliver 20dBm and meet an ACPR specification of -30dBc in the 2.4 to 2.5GHz ISM band. The efficiency of this two stage RFPA can be optimized by adjusting the bias current with a dedicated resistor when lower power output is used. No external positive or negative power supplies are required to set the bias currents. The on chip bias network provides the optimum bias current temperature compensation when low TC external resistor is used. To get the best performance from the ISL3985, the output stage matching network can be tailored using external components.
2
ISL3985
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . . -0.3 to VCC +0.3V VCC to VCC Decouple . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Any GND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) QFN Package. . . . . . . . . . . . . . . . . . . . 33 3 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC For Recommended soldering conditions see Tech Brief TB389.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85oC Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.6V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. JC, the "case temp" is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
General DC Electrical Specifications, TA = 25oC
PARAMETER Supply Voltage Total Power Amplifier Supply Current at 3.3V, 21dBm Output RF Detector Supply Current Power Down Supply Current Power Up/ Down Speed CMOS Low Level Input Voltage CMOS High Level Input Voltage (VDD = 3.6V) CMOS Threshold Voltage CMOS High or Low Level Input Current MIN 2.7 0. 7 * V D D >0.3*VDD -10 TYP 325 1. 4 30 230 0.5*VDD MAX 3.6 360 2.0 0.3*V D D 4 <0.7*VDD +10 UNITS V mA mA µA ns V V V µA
Power Amplifier AC Electrical Specifications VCC = 3.3V, f = 2.45GHz, Unless Otherwise Specified. Typical Application Circuit
(external input and output matching networks) have been used. TA = 25oC TEST CONDITIONS MIN 24 00 25.0 ACPR, DSSS, 1st Side Lobe <-30dBc, 2nd Side Lobe <-50dBc Output Spurs Less than -60dBc (Note 2) 19.5 T YP 26.5 21 5.5 20.7 MAX 2500 2 8 .0 2 :1 3 :1 1 0 :1 10 :1 PARAMET ER RF Frequency Range Power/Voltage Gain Output P1dB AM to PM @ compression Input 50 VSWR Output 50 VSWR Output Power Output Stability VSWR Output Load Mismatch NOTE: 2. Devices sustain no damage when subjected to a mismatch of maximum 10:1. U NITS MH z dB dB m Degrees dBm -
Peak Detector AC Electrical Specifications TA = 25oC
PARAMETER RF Output Detector Response Time RF Output Detector Voltage Range RF Output Detector Linearity TEST CONDITIONS External Capacitor, C = 5pF Load > 1M Over Linear Range TEMP. (oC) Full Full Full MIN 0 - 0.5 T YP 0. 15 MAX 1 .5 +0.5 UNITS µs V dB/V
3
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