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Part: IS71V08F32ESB08-7070BI
Category:
Memory
-> Multi Chip Memory
-> Flash + SRAM
Description:
Company: Integrated Silicon Solution Inc.
Datasheet: Download IS71V08F32ESB08-7070BI datasheet File size : 118 kB
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Datasheet text preview:
IS71V08F32ESx08 IS71V16F32ESx08
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip Package (MCP) -- 32 Mbit Simultaneous Operation Flash Memory and 8 Mbit Static RAM
ISSI
· Program Algorithms:
Automatically writes and verifies data at specified address
®
PRELIMINARY INFORMATION OCTOBER 2002
MCP FEATURES
· Power supply voltage 2.7V to 3.3V · High performance:
Flash: 70ns maximum access time SRAM: 70ns maximum access time
· Hidden ROM Region:
256 byte with a Factory-serialized secure electronic serial number (ESN), which is accessible through a command sequence
· Package: 73-ball BGA · Operating Temperature: -40C to +85C
FLASH FEATURES · Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum Read Current at 5 Mhz: 18 mA maximum Sleep Mode: 5 µA maximum
· Data Polling and Toggle Bit:
Allow for detection of program or erase cycle completion
· Ready-Busy output (RY/BY): Detection
of program or erase cycle completion
· Simultaneous Read and Write Operations:
Zero latency between read and write operations; Data can be programmed or erased in one bank while data is simultaneously being read from the other bank
· Over 100,000 write/erase cycles · Low supply voltage (Vccf 2.5V) inhibits writes · WP/ACC input pin:
If VIL, allows protection of boot sectors If VIH, allows removal of boot sector protection If Vacc, program time is reduced by 40%
· Low-Power Mode:
A period of no activity causes flash to enter a low-power state
· Boot sector: Top or Bottom
· Erase Suspend/Resume:
Suspends of erase activity to allow a read in the same bank
SRAM FEATURES (8 Mb density) · Power Dissipation:
Operating: 25 mA maximum Standby: 15 µA maximum Chip Selects: CE1s, CE2s Power down feature using CE1s, or CE2s Data retention supply voltage: 1.2 to 3.3 volt Byte data control: LBs (DQ0DQ7), UBs (DQ8DQ15) -- in x16 version
· Sector Erase Architecture:
8 sectors of 4k words each and 63 sectors of 32K words each in Word Mode, or 8 sectors of 8k bytes each and 63 sectors of 64K bytes each in Byte Mode · Erase Algorithms: Automatically preprograms/erases the flash memory entirely, or by sector
· · · ·
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 10/21/02
1
IS71V08F32ESX08 IS71V16F32ESx08
ISSI
®
GENERAL DESCRIPTION
The flash and SRAM MCP is a 32 Mbit Flash/8 Mbit SRAM data bus. The 32 Mbit flash is composed of 2,097,152 words of 16 bits or 4,194,304 bytes of 8 bits. The SRAM has 524,288 words of 16 bits or 1,048,576 bytes of 8 bits. The Flash memory in Word mode (or x16 version of SRAM) is accessed with data lines DQ0-DQ15. The Flash memory in Byte mode ( or x8 version of SRAM) is accessed by data lines DQ0 - DQ7. Single byte SRAM data access can be accomplished by using LBs or UBs, and DQ0 - DQ7 or DQ8-DQ15, respectively. The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations. The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM programmer. The 32 Mbit flash/8 Mbit SRAM is offered in a 73-pin BGA package. The flash is compatible with the JEDEC Flash command set standard . The flash access time is 70ns and the SRAM access time is 70ns. The Flash architecture is composed of two virtual banks which allows simultaneous operation on each. Optimized performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. Both operations would then be operating simultaneously, with zero latency.
MCP BLOCK DIAGRAM
VCCf A0-A20 A0-A20 A-1 WP/ACC RESET CEf I/Of
GND
RY/BY
32-MBIT Flash Memory DQ0-DQ15/A-1
VCCS GND A0-A18 SA LBs UBs WE OE CE1s CE2s 8-MBIT Static RAM DQ0-DQ15
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 10/21/02
IS71V08F32ESX08 IS71V16F32ESx08
LOGIC SYMBOL
22 A0-A20, A-1 CEf CE1s CE2s OE WE WP/ACC RESET UBs LBs I/Of SA DQ0-DQ15 16 or 8 RY/BY
ISSI
®
FLASH MEMORY BLOCK DIAGRAM
VCC GND A0-A20 Upper Bank Address Y-Decoder RY/BY A0-A20 RESET WE CE I/of WP/ACC DQ0-DQ15 A0-A20 Lower Bank Latches and Control Logic STATE CONTROL & COMMAND REGISTER Control DQ0-DQ15 A0-A20 X-Decoder DQ0-DQ15 DQ0-DQ15 Upper Bank Latches and Control Logic OE I/of
Status
A0-A20
Lower Bank Address
Y-Decoder
X-Decoder OE I/of
FLASH BANK ORGANIZATION
Organization Type Dual Bank Dual Bank Note:
For complete device part number, see Part Number Logic Diagram or ordering information
Bank 1 Size 8Mb 8Mb
Bank 2 Size 24Mb 24Mb
Boot Block Top Bottom
Part Number IS71V16F32EST08 IS71V16F32ESB08
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 10/21/02
3
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