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Part: IS61SPD25636T-166TQ
Category:
Memory
-> SRAM
-> Sync. SRAM
Description: 256Kx36
Company: Integrated Silicon Solution Inc.
Datasheet: Download IS61SPD25636T-166TQ datasheet File size : 468 kB
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IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM
FEATURES
· Internal self-timed write cycle · Individual Byte Write Control and Global Write · Clock controlled, registered address, data and control · PentiumTM or linear burst sequence control using MODE input · Three chip enable option for simple depth expansion and address pipelining · Common data inputs and data outputs · JEDEC 100-Pin TQFP and 119-pin PBGA package · Single +3.3V, +10%, 5% power supply · Power-down snooze mode · 3.3V I/O For SPD · 2.5V I/O For LPD · Double cycle deselect · Snooze MODE for reduced-power standby · T version (three chip selects) · D version (two chip selects)
ISSI
®
PRELIMINARY INFORMATION SEPTEMBER 2000
DESCRIPTION The ISSI IS61SPD25632, IS61SPD25636, S61SPD51218,
IS61LPD25632, IS61LPD25636, and IS61LPD51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, secondary cache for the PentiumTM, 680X0TM, and PowerPCTM microprocessors. The IS61SPD25632 and IS61LPD25632 are organized as 262,144 words by 32 bits and the IS61SPD25636 and IS61LPD25636 are organized as 262,144 words by 36 bits. The IS61SPD51218 and IS61LPS51218 are organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol t KQ tKC Parameter Clock Access Time Cycle Time Frequency -166* 3.5 6 166 -150 3.8 6.7 150 -133 4 7.5 133 -5 5 10 100 Units ns ns MHz
*This speed available only in SPD version
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
1
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
BLOCK DIAGRAM
MODE Q0 A0'
ISSI
A1'
®
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP A18-A0 (61SPD51218, 61LPD51218) A17-A0 (61SPD25632/36, 61LPD25632/36) CE CLR Q1 A1
256Kx32; 256Kx36; 512Kx18 MEMORY ARRAY
16/17 18/19 Q
18/19 D
ADDRESS REGISTER
CE CLK 32, 36, or 18 32, 36, or 18
GW BWE BWd (x32/x36)
DQd BYTE WRITE REGISTERS
CLK
D
Q
BWc (x32/x36)
D DQc Q BYTE WRITE REGISTERS CLK
BWb (x32/x36/x18)
DQb BYTE WRITE REGISTERS
CLK
D
Q
BWa (x32/x36/x18)
D DQa Q BYTE WRITE REGISTERS CLK
(T, D) CE (T, D) CE2 (T) CE2 D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK OE
32, 36, or 18 DQa - DQd
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
PIN CONFIGURATION
119-pin PBGA (Top View)
1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ NC A10 A11 A14 NC ZZ A5 MODE VCC NC A13 NC NC GND A0 GND NC DQa1 DQd7 GND A1 GND DQa3 DQa2 DQd5 GND DQd3 DQd2 GND BWd CLK NC BWE GND BWa GND DQa7 DQa5 DQa4 DQa8 DQa6 VCCQ VCC NC VCC NC VCC VCCQ DQc8 GND DQc6 DQc4 GND BWc DQc3 GND NC GND NC CE OE ADV GW GND GND GND BWb GND NC DQb6 DQb5 DQb4 DQb2 DQb8 DQb7 VCCQ DQb3 DQb1 A7 A2 VCC A12 A15 NC CE2 A3 A6 A4 2 3 4 5 6 7
ISSI
100-Pin TQFP (D Version)
A6 A7 CE CE2 BWd BWc BWb BWa A17 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
®
ADSP ADSC
A8 A9
A16 A17
VCCQ NC
NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ GNDQ GW CE, CE2 OE DQa-DQd MODE VCC GND VCCQ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Isolated Output Buffer Ground
A2-A17 CLK ADSP ADSC ADV BWa-BWd BWE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
3
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