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Part: IS42S16128-10
Category:
Memory
-> DRAM
Description: 256Kx16 (4-MBIT) Synchronous Dynamic RAM
Company: Integrated Silicon Solution Inc.
Datasheet: Download IS42S16128-10 datasheet File size : 808 kB
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Datasheet text preview:
IS42S16128
128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
· Clock frequency: 125 MHz, 100 MHz, 83 MHz · Two banks can be operated simultaneously and independently · Single 3.3V power supply · LVTTL interface · Programmable burst length (1, 2, 4, 8, full page) · Programmable burst sequence: Sequential/Interleave · Auto refresh, self refresh · 1K refresh cycles every 16 ms · Random column address every clock cycle · Programmable CAS latency (2, 3 clocks) · Burst read/write and burst read/single write operations capability · Byte controlled by LDQM and UDQM · Package 400-mil 50-pin TSOP II
ISSI
DESCRIPTION PIN DESCRIPTIONS
A0-A9 A0-A8 A9 A0-A7 I/O0 to I/O15 CLK CKE CS RAS CAS WE LDQM UDQM Address Input Row Address Input Bank Select Address Column Address Input Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection
®
FEBRUARY 2000
ISSI's 4Mb Synchronous DRAM IS42S16128 is organized as a 131072-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VCC I/O0 I/O1 GNDQ I/O2 I/O3 VCCQ I/O4 I/O5 GNDQ I/O6 I/O7 VCCQ LDQM WE CAS RAS CS A9 A8 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GND I/O15 I/O14 GNDQ I/O13 I/O12 VCCQ I/O11 I/O10 GNDQ I/O9 I/O8 VCCQ NC UDQM CLK CKE NC NC NC A7 A6 A5 A4 GND
Vcc GND VccQ GNDQ NC
ORDERING INFORMATION Commercial Range: 0C to 70C
Frequency 125 MHz 100 MHz 83 MHz Speed (ns) 8 10 12 Order Part No. IS42S16128-8T IS42S16128-10T IS42S16128-12T Package 400-mil TSOP II 400-mil TSOP II 400-mil TSOP II
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
03/13/00
1
IS42S16128
PIN FUNCTIONS
Pin No. 20 to 24, 27 to 30 Symbol A0-A8 Type Input Pin Function (In Detail)
ISSI
®
19
A9
Input Pin
16 34
CAS CKE
Input Pin Input Pin
35 18
CLK CS
Input Pin Input Pin
2, 3, 5, 6, 8, 9, 11 12, 39, 40, 42, 43, 45, 46, 48, 49 14, 36
I/O0 to I/O15 LDQM, UDQM
I/O Pin
A0 to A8 are address inputs. A0-A8 are used as row address inputs during active command input and A0-A7 as column address inputs during read or write command input. A8 is also used to determine the precharge mode during other commands. If A8 is LOW during precharge command, the bank selected by A9 is precharged, but if A8 is HIGH, both banks will be precharged. When A8 is HIGH in read or write command cycle, the precharge starts automatically after the burst access. These signals become part of the OP CODE during mode register set command input. A9 is the bank selection signal. When A9 is LOW, bank 0 is selected and when high, bank 1 is selected. This signal becomes part of the OP CODE during mode register set command input. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. The CKE input determines whether the CLK input is enabled within the device. When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid. When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and UDQM pins. LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VCCQ is the output buffer power supply. VCC is the device internal power supply. GNDQ is the output buffer ground. GND is the device internal ground.
Input Pin
17 15 7, 13, 38, 44 1, 25 4, 10, 41, 47 26, 50
RAS WE VCCQ VCC GND Q GND
Input Pin Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/13/00
IS42S16128
FUNCTIONAL BLOCK DIAGRAM
CLK CKE CS RAS CAS WE A9
ISSI
COMMAND DECODER & CLOCK GENERATOR
ROW DECODER
®
MODE REGISTER
9
9
ROW ADDRESS BUFFER
MEMORY CELL ARRAY
512
9
BANK 0
DQM
SENSE AMP I/O GATE
A8
8
COLUMN ADDRESS BUFFER
BURST COUNTER
COLUMN ADDRESS LATCH
DATA IN BUFFER
16 16
256x16
COLUMN DECODER
ROW DECODER
MULTIPLEXER
A7 A6 A5 A4 A3 A2 A1 A0
REFRESH CONTROLLER
SELF REFRESH CONTROLLER
I/O 0-15
8 256x16
SENSE AMP I/O GATE
REFRESH COUNTER
DATA OUT BUFFER
16 16
9
ROW ADDRESS LATCH
9
ROW ADDRESS BUFFER
512
MEMORY CELL ARRAY
Vcc/VccQ GND/GNDQ
BANK 1
9
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A
03/13/00
3
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