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Part: PEELTM22LV10AZ
Category:
FPGAs/PLDs
-> PLDs (Programmable Logic Devices)
-> SPLDs (Simple PLD)
-> Other Families
Description:
Company: Integrated Circuit Technology Corp.
Datasheet: Download PEELTM22LV10AZ datasheet File size : 498 kB
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Datasheet text preview:
Commercial/Industrial
PEELTM 22LV10AZ-25 / I-35 CMOS Programmable Electrically Erasable Logic Device
Features
ˇ Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc = 5 ľA (typical) at standby - Icc = 1.5 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-B) - 5 Volt tolerant inputs and I/O's CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Application Versatility - Replaces random logic - Super set of standard PLDs - Pin and JEDEC compatible with 22V10 - Ideal for battery powered systems - Replaces expensive oscillators ˇ ˇ Architectural Flexibility - Enhanced architecture fits in more logic - 133 product terms x 44 input AND array - 12 inputs and 10 I/O pins - 12 possible macrocell configurations - Asynchronous clear, synchronous preset - Independent output enables - Programmable clock; pin 1 or p-term - Programmable clock polarity - 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC - Schmitt triggers on clock and data inputs Schmitt Trigger Inputs - Eliminates external Schmitt trigger devices - Ideal for encoder designs
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General Description
The PEEL22LV10AZ is a Programmable Electrically Erasable Logic (PEEL) SPLD (Simple Programmable Logic Device) that operates over the supply voltage range of 2.7V-3.6V and features ultra-low, automatic "zero" power-down operation. The PEEL22LV10AZ is logically and functionally similar to ICT's 5V PEEL22CV10A and PEEL22CV10AZ. The "zero power" (25 ľA max. ICC) power-down mode makes the PEEL22LV10AZ ideal for a broad range of batterypowered portable equipment applications, from handheld meters to PCMCIA modems. EEreprogrammability provides both the convenience of product fast reprogramming for product development and quick personalization in manufacturing, including Engineering Change Orders. Figure 1 - Pin Configuration
I/C L K I I I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/C L K I I I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
The differences between the PEEL22LV10AZ and PEEL22CV10A include the addition of programmable clock polarity, p-term clock, and Schmitt trigger input buffers on all inputs, including the clock. Schmitt trigger inputs allow direct input of slow signals such as biomedical and sine waves or clocks. Like the PEEL22CV10A, the PEEL22LV10AZ is a pin and JEDEC compatible, logical superset of the industry standard PAL22V10 SPLD Figure 1. The PEEL22LV10AZ provides additional architectural features that allow more logic to be incorporated into the design. The PEEL22LV10AZ architecture allows it to replace over twenty standard 24-pin DIP, SOIC, TSSOP and PLCC packages. Figure 2 - Block Diagram
C L K MUX (O p t i o n a l )
I I I NC I I I
4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18
I I I/C L K NC VCC I/O I/O
D IP
TSSOP
I/C L K I I I I I I I I I I I
SP AC PEEL "AN D " AR R A Y
TM
OE MACRO C EL L I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
1 3 3 Terms X 4 4 Inp u t s
I/O I/O I/O NC I/O I/O I/O
I I GND NC I I/O I/O
I/C L K I I I I I I I I I I GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
S P = SYNCHRONO U S PRESET A C = ASYNCHRONO U S CLEAR O E = O U T P U T ENABLE
P LCC
S O IC
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PEELTM 22LV10AZ
(
132 0
N ASYNC RONOUS CLEAR H (TO A LL MA C OCE LLS) R
2
9
MACRO CELL
I/O*
(27)
I/CLK*
(2)
10
20
MACRO CELL
I/O*
(26)
I*
(3)
21
MACRO CELL
33
I/O*
(25)
I*
(4)
34
MACRO CELL
48
I/O*
(24)
I*
49
(5)
MACRO CELL
65
I/O*
(23)
I*
(6)
66
MACRO CELL
82
I/O*
(21)
I*
(7)
83
MACRO CELL
97
I/O*
(20)
I*
(9)
98
MACRO CELL
110
I/O*
(19)
I*
(10)
111
121
MACRO CELL
I/O*
(18)
I*
(11)
124
130
I*
(12)
131
MACRO CELL
SYNCHRONO S PRESET U (TO A LL MA C OCE LLS) R
I/O*
(17)
I*
(13)
I* * Schmitt Trigger Inputs
(16)
Figure 3 - PEEL22LV10AZ Logic Array Diagram
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PEELTM 22LV10AZ Function Description
The PEEL22LV10AZ implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility. ICT has added optional enhanced capabilities to the PEEL22CV10A family of products with additional features and added fuses to support them. Please view the comparison chart found below for the best algorithm Algorithms Number of Fuses Supported Features PEEL V10A Algorithm 5828 Standard 22V10 JEDEC Compatible 4 macrocell options PEEL V10A+ Algorithm 5873 Superset of standard 22V10 12 macrocell options 3 byte signature word Security bit PEEL V10A++ Algorithm 5958 Superset of standard 22V10 (recommended for new designs) 12 macrocell options 8 byte signature word Security bit Clock source selection Clock polarity selection Table 1 - Programming Algorithm Comparison
Architecture Overview The PEEL22LV10AZ architecture is illustrated in the block diagram of Figure 2. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creation of logic functions. At the core of the device is a programmable electrically erasable AND array that drives a fixed OR array. With this structure, the PEEL22LV10AZ can implement up to 10 sum-ofproducts logic expressions. Associated with each of the ten OR functions is an I/O macrocell that can be independently programmed to one of 12 different configurations, including the four standard 22V10 modes. The programmable macrocells allow each I/O to be used to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the AND array. AND/OR Logic Array The programmable AND array of the PEEL22LV10AZ (shown in Figure 3) is formed by input lines intersecting product terms. The input lines and product terms are used as follows: ˇ 44 Input Lines: - 24 input lines carry the true and complement of the signals applied to the 12 input pins - 20 additional lines carry the true and complement values of feedback or input signals from the 10 I/Os
ˇ 133 Product Terms: - 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) are used to form sum of product functions - 10 outputs enable terms (one for each I/O) - 1 global synchronous preset term - 1 global asynchronous clear term - 1 programmable clock term At each input-line/product-term intersection, there is an EEPROM memory cell that determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term that is connected to both the true and complement of an input signal will always be FALSE and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a "don't care" state exists and that term will always be TRUE. When programming the PEEL22LV10AZ, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEEL device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function).
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