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Part: PEELTM18CV8Z
Category:
FPGAs/PLDs
-> PLDs (Programmable Logic Devices)
-> SPLDs (Simple PLD)
-> Other Families
Description:
Company: Integrated Circuit Technology Corp.
Datasheet: Download PEELTM18CV8Z datasheet File size : 498 kB
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Datasheet text preview:
Commercial PEELTM 18CV8Z-25 CMOS Programmable Electrically Erasable Logic Device
Features
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Ultra Low Power Operation - Vcc = 5 Volts ±10% - Icc = 10 µA (typical) at standby - Icc = 2 mA (typical) at 1 MHz CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Application Versatility - Replaces random logic - Super set of standard PLDs - Pin-to-pin compatible with 16V8 - Ideal for use in power-sensitive systems
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Architectural Flexibility - Enhanced architecture fits in more logic - 113 product terms x 36 input AND array - 10 inputs and 8 I/O pins - 12 possible macrocell configurations - Asynchronous clear, Synchronous preset - Independent output enables - Programmable clock; pin 1 or p-term - Programmable clock polarity - 20 Pin DIP/SOIC/TSSOP and PLCC
General Description
The PEELTM18CV8Z is a Programmable Electrically Erasable Logic (PEELTM) SPLD (Simple Programmable Logic Device) that features ultra-low, automatic "zero" power-down operation. The "zero power" (100 µA max. Icc) power-down mode makes the PEELTM18CV8Z ideal for a broad range of battery-powered portable equipment applications, from hand-held meters to PCMCIA modems. EE-reprogrammability provides both the convenience of fast reprogramming for product development and quick product personalization in manufacturing, including Engineering Change Orders. The PEELTM18CV8Z is logically and functionally similar to ICT's 5 Volt PEELTM18CV8 and 3 Volt PEELTM18LV8Z. The differences between the PEELTM18CV8Z and PEELTM18CV8 include the addition of programmable clock polarity, a product term clock, and variable width product terms in the AND/OR Logic Array. Like the PEELTM18CV8, the PEELTM18CV8Z is logical superset of the industry standard PAL16V8 SPLD. The PEELTM18CV8Z provides additional architectural features that allow more logic to be incorporated into the design. ICT's JEDEC file translator allows easy conversion of existing 20 pin PLD designs to the PEELTM18CV8Z architecture without the need for redesign. The PEELTM18CV8Z architecture allows it to replace over twenty standard 20-pin DIP, SOIC, TSSOP and PLCC packages.
Figure 7 Pin Configuration
I/CLK I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC I/O I/O I/O I/O I/O I/O I/O I/O I
Figure 8 Block Diagram
CLK MUX (Optional)
DIP
TS SOP
TM
PLCC
SOIC
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PEELTM 18CV8Z-25
(OPTIONAL)
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35
112 0 1 2
ASYNCHRONOUS CLEAR (TO ALL MACROCELLS)
9
MACRO CELL
19
I/O
I/CLK
1
10 11
20
MACRO CELL
18
I/O
I
2
21 22
MACRO CELL
33
17
I/O
I
3
34 35
MACRO CELL
48
16
I/O
I
4
49 50
I/O MACRO CELL
65
15
I
5
66 67
I/O MACRO CELL
82
14
I
6
83 84
MACRO CELL
97
13
I/O
I
7
98 99
MACRO CELL
110
12
I/O
I I
8
111
SYNCHRONOUS PRESET (TO ALL MACROCELLS)
9
11
I
Figure 9 PEELTM18CV8Z Logic Array Diagram
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PEELTM 18CV8Z-25
Function Description
The PEELTM18CV8Z implements logic functions as sum-ofproducts expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility. effect on the output function).
Variable Product Term Distribution
The PEELTM18CV8Z provides 113 product terms to drive the eight OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Figure 9). This distribution allows optimum use of the device resources.
Architecture Overview
The PEELTM18CV8Z architecture is illustrated in the block diagram of Figure 8. Ten dedicated inputs and 8 I/Os provide up to 18 inputs and 8 outputs for creation of logic functions. At the core of the device is a programmable electrically-erasable AND array that drives a fixed OR array. With this structure, the PEELTM18CV8Z can implement up to eight sum-of-products logic expressions. Associated with each of the eight OR functions is an I/O macrocell that can be independently programmed to one of 12 different configurations. The programmable macrocells allow each I/O to be used to create sequential or combinatorial logic functions of active-high or active-low polarity, while providing three different feedback paths into the AND array.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently lets you to tailor the configuration of the PEELTM18CV8Z to the precise requirements of your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 9, consists of a D-type flip-flop and two signal-select multiplexers. The configuration of each macrocell is determined by the four EEPROM bits controlling these multiplexers. These bits determine output polarity, output type (registered or non-registered) and input-feedback path (bidirectional I/O, combinatorial feedback). Refer to Table 1 for details. Equivalent circuits for the twelve macrocell configurations are illustrated in Figure 11. In addition to emulating the four PALtype output structures (configurations 3, 4, 9, and 10), the macrocell provides eight additional configurations. When creating a PEELTM device design, the desired macrocell configuration is generally specified explicitly in the design file. When the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the JEDEC programming file.
AND/OR Logic Array
The programmable AND array of the PEELTM18CV8Z (shown in Figure 9) is formed by input lines intersecting product terms. The input lines and product terms are used as follows:
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36 Input Lines: 20 input lines carry the true and complement of the signals applied to the 10 input pins 16 additional lines carry the true and complement values of feedback or input signals from the 8 I/Os 113 product terms: 102 product terms are used to form sum of product functions 8 output enable terms (one for each I/O) 1 global synchronous preset term 1 global asynchronous clear term 1 programmable clock term
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Output Type
The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register is set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear sets Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset.
At each input-line/product-term intersection, there is an EEPROM memory cell that determines whether or not there is a logical connection at that intersection. Each product term is essentially a 36-input AND gate. A product term that is connected to both the true and complement of an input signal will always be FALSE and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a "don't care" state exists and that term will always be TRUE. When programming the PEELTM18CV8Z, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEELTM device programmers automatically program all of the connections on unused product terms so that they will have no
Output Polarity
Each macrocell can be configured to implement active-high or active-low logic. Programmable polarity eliminates the need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to
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