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Part: HYS72V32501/600GR
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> 256 MB
Description:
Company: Infineon Technologies Corporation
Datasheet: Download HYS72V32501/600GR datasheet File size : 2898 kB
Request For quote: Find where to buy HYS72V32501/600GR
Datasheet text preview:
HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules
3.3 V Low Profile 168-pin PC133 Registered SDRAM Modules for 1U Server Applications PC133 128 MByte Module PC133 256 MByte module PC133 512 MByte Module PC133 1024 MByte Module
· 168-pin Registered 8 B yte Dual-In-Line SDRAM Module for Workstation and Server main memory applications with 1,2" inch (30,40 mm) height · One bank 16M × 72, 32M x 72 and 64M × 72 and two bank 128Mx72 organization · Optimized for ECC applications with very low input capacitances · JEDEC standard Synchronous DRAMs (SDRAM) with 128Mb, 256Mb and 512Mb memory density. Stacked components for two bank modules · Single + 3.3 V (± 0.3 V) power supply · Auto Refresh (CBR) and Self Refresh · Serial Presence Detect with E 2PR OM
PreliminaryData Sheet Rev. 0.9 (9/01)
· Pr ogrammable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) · All inputs and outputs are LVTTL compatible · Utilizes SDRAMs in TSOPII-54 packages with on-board registers and PLL. · Card Sizes : RawCard "F" and "G" 133.35 mm x 30,40 with gold contact pads · These modules all fully compatible with the current industry standard PC133 specifications and fully backward compatible to PC100 applications
· Performance: -7.5
f CK 3 t A C3 f CK 2 t A C2
Unit M Hz ns M Hz ns
Clock Frequency (max.) @ CL = 3 Clock Access Time (min.)@ CL = 3 Clock Frequency (max.) @ CL = 2 Clock Access Time (min.)@ CL = 2
133 5.4 100 6
The HYS 72Vxx5 /6x0GR-7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) orga nized as 16M × 72, 32M x 72, 64M × 72 and 128M x 72 high speed memory arrays designed with x4 or x8 orga nised Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on -DIMM and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacit ive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacit ors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM using the 2-pin I2C protocol. The first 128 byte s are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint. This module family is designed with 30,40 mm (1.2 inch) maximum he igh t for 1U Server Applications b ased on JEDEC standard RawCards "F" and "G".
INFINEON Technologies
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HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules
Ordering Information Type 1.2" height: HYS 72V16600GR-7.5 HYS 72V32501GR-7.5 HYS 72V32600GR-7.5 HYS 72V64500GR -7.5 HYS 72V64601GR -7.5 PC 133R-333-542- F PC 133R-333-542- G PC 133R-333-542- F PC 133R-333-542- G PC 133R-333-542- F one bank 128 MB Reg. DIMM one bank 256 MB Reg. DIMM one bank 256 MB Reg. DIMM one bank 512 MB Reg. DIMM one bank 512 MB Reg. DIMM two banks 1024 MB Reg. DIMM 128 MBit (x8) 128 MBit (x4) 256 Mbit (x8) 256 Mbit (x4) 512 MBit (x8) 256 Mbit (x4) stacked Compliance Code Description SDRAM Technology
HYS 72V128520GR-7.5 PC 133R-333-542- G
Note:
All part numbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS 64V16600 GR-7.5 -C2, indicating Rev.C2 dies are used for SDRAM comp onents.
INFINE ON Technologies
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HYS 72Vxx5/6x0GR-7.5 Low Profile PC133 Registered SDRAM-Modules
Pin Definitions and Functions A0 - A11, A12 A ddress Inputs
(A12 is used for 256Mbit and 512Mbit based modules only)
DQMB0 - DQMB7 Data Mask
BA0, BA1 DQ0 - DQ63
B ank Selects Data Input/Output
CS0 - CS3 REGE *)
Chip Select Register Enable
"H" or N.C = registered mode "L" = buffered mode
CB0 - CB7 RAS CAS WE CKE0
Check Bits Row Address Strobe Column Address Strobe Read/Write Input Clock Enable
VDD VS S
SCL SDA N.C.
Power (+ 3.3 V) Ground Clock for Presence Detect Serial Data Out No Connection
CLK0 - CLK3 Clock Input
*) note : To confirm to this specification, motherboards must pull this pin to high state or no connect.
Address Format Density Organization Memory SDRAMs Banks 128 MB 16M × 72 256 MB 32M x 72 256 MB 32M x 72 512 MB 64M × 72 512 MB 64M × 72 1 GB 128M x 72 1 1 1 1 1 2 16M x 8 32M x 4 32M x 8 64M × 4 64M × 8 64M × 4 # of # of row/bank/ Refresh Period Interval SD RAMs columns bits 9 18 9 18 9 36 12/2/10 12/2/11 13/2/10 13/2/11 13/2/12 13/2/11 4k 4k 8k 8k 8k 8k 64 ms 15.6 µs 64 ms 15.6 µs 64 ms 7.8 µs 64 ms 7.8 µs 64 ms 7.8 µs 64 ms 7.8 µs
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