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Part: HYS72V32300GR-7-D
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> 256 MB
Description: 128MB - 2GB, 168pin
Company: Infineon Technologies Corporation
Datasheet: Download HYS72V32300GR-7-D datasheet File size : 2898 kB
Request For quote: Find where to buy HYS72V32300GR-7-D
Datasheet text preview:
HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules 3.3 V 168-pin R egistered SDRAM Modules PC133 128 MByte Module PC133 256 MByte module PC133 512 MByte Module PC133 1 GByte Module PC133 2 GByte Module
· 168-pin Registered 8 B yte Dual-In-Line SDRA M Module for PC and Server main memory applications · One bank 16M × 72, 32M x 72, 64M × 72and 128M x 72, two bank 128M × 72 and 256M x 72 organization · Optimized for ECC applications with very low input capacitances · JEDEC standar d S ynchronous DRAMs (SDRA M) Progr ammable CAS Latency, Bur st Length and Wrap Sequence (Sequential & Interleave) · Single + 3.3 V (± 0.3 V) power supply · Auto Refresh (CBR) and S elf Refresh · Performance: speed grade
fCK tCK tAC fCK tCK tAC Clock Freque ncy (max.) @ CL = 3 Clock Cycle Time (min.) @ CL = 3 Clock Access Time (min.) @ CL= 3 Clock Freque ncy (max.) @ CL = 2 Clock Cycle Time (min.) @ CL = 2 Clock Access Time (min.) @ CL= 2
· Pr ogrammable CAS Latency, Burst Length, and Wr ap Sequence (Sequential & Interleave) · All inputs and outputs are LVTTL compatible · Serial Presence Detect with E2P ROM · Utilizes SDRAMs in TSOPII- 54 packages with registers and PLL. · Card Size: 133.35 mm × 38.10 / 43.18 mm with Gold contact pads and max. 4.00 / 6.80 mm thickness (JEDEC MO-161) · These modules all fully compatible with the curr ent industry standard PC133 and PC100 specifications
-7
133 7.5 5.4 133 7.5 5.4
-7.5
133 7.5 5.4 100 10 6
Unit
MHz ns ns MHz ns ns
Description
The HYS 7 2Vxx3xxGR-7 and -7.5 are indu stry stand ard 168-pin 8-b yte Du al in-lin e Memo ry Modu les (DI MMs) orga nized as 16M × 7 2, 32M x 72, 64M × 72, 128 M × 72 an d 256M x 72 hig h spe ed memory arra ys designe d with Synchronou s DRAMs (SDRAMs) f or ECC a pplication s. All control and address signals a re registered on-DIMM an d the design incorporates a PLL circuit for the Clo ck in puts. Use of a n on-boa rd re gister reduces ca pacitive loading on the inpu t sign als b ut a re delaye d b y one cycle in arriving at t he SDRAM devices. De cou pling cap acitors are moun ted o n the PC board. The DIMMs u se a serial presence de tect s scheme imp lemented via a serial E2PROM using the 2-pin I 2C protocol. Th e first 128 b yte s are utilize d by the DIMM manu fact ure r a nd the second 12 8 bytes are ava ilable to the end user. All In fine on 168-pin DIMMs provid e a high pe rforma nce , flexib le 8 -byte interface in a 133 .35 mm lo ng foot print.
INFINEON Technologies
1
2002-07-18
HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules
Ordering Inf ormation Partnumber 1) PC133-333:
HYS 72V16300 GR-7.5 -C HYS 72V16300 GR-7.5 -E HYS 72V16301 GR-7.5 -C2 HYS 72V32301 GR-7.5 -C2 HYS 72V32300 GR-7.5 -C2 HYS 72V32300 GR-7.5 -D HYS 72V64300 GR-7.5 -C2 HYS 72V64300 GR-7.5 -D PC133R-333 -54 2-B2 o ne ba nk 1 28 MB Reg. DI MM PC133R-333 -54 2-B2 o ne ba nk 1 28 MB Reg. DI MM PC133R-333 -54 2-B2 o ne ba nk 2 56 MB Reg. DI MM PC133R-333 -54 2-AA o ne ba nk 2 56 MB Reg. DI MM PC133R-333 -54 2-B2 o ne ba nk 5 12 MB Reg. DI MM 64 MBit (x4) 128 MBit (x8) 128 Mb it (x4) 256 Mb it (x8) 256 MBit (x4) 256 MBit (x4, stacked) 3) 512 MBit (x4) 512 MBit (x4, stacked) 3)
Compliance Code 2)
D escription
S DRAM Technology
HYS 72V12832 0/1GR-7.5-C2 PC133R-333 -54 2-B2 t wo banks 1 GByte Reg. DIMM HYS 72V12832 0/1GR-7.5-D HYS 72V12830 0GR -7. 5-A HYS 72V25632 0/1GR-7.5-A PC133R-333 -54 2-B2 o ne ba nk 1 GByte Reg. DIMM PC133R-333 -54 2-B2 t wo banks 2 GByte Reg. DIMM
PC133-222:
HYS 72V16300 GR-7-E HYS 72V16301 GR-7-C2 HYS 72V32301 GR-7-C2 HYS 72V32300 GR-7-D HYS 72V64300 GR-7-D HYS 72V12832 0/1GR-7-D HYS 72V12830 0GR -7-A HYS 72V25632 0/1GR-7-A PC133R-222 -54 2-B2 o ne ba nk 1 28 MB Reg. DI MM PC133R-222 -54 2-B2 o ne ba nk 1 28 MB Reg. DI MM PC133R-222 -54 2-B2 o ne ba nk 2 56 MB Reg. DI MM PC133R-222 -54 2-AA o ne ba nk 2 56 MB Reg. DI MM PC133R-222 -54 2-B2 o ne ba nk 5 12 MB Reg. DI MM PC133R-222 -54 2-B2 t wo banks 1 GByte Reg. DIMM PC133R-222 -54 2-B2 o ne ba nk 1 GByte Reg. DIMM PC133R-222 -54 2-B2 t wo banks 2 GByte Reg. DIMM 64 MBit (x4) 128 MBit (x8) 128 Mb it (x4) 256 Mb it (x8) 256 MBit (x4) 256 MBit (x4, stacked) 3) 512 MBit (x4) 512 MBit (x4, stacked) 3)
Note s: 1.) All part numbers e nd wit h a place co de, de signating the die re vision of the compon ents used on t he Re gistered DIMM mod ule . Consult facto ry for curren t re vision. Example : HYS 64V32300 GR-7.5-D, indicat ing Rev.D dies are used f or 2 56Mb it SDRAM comp onents. 2.) The Compliance Co de is printed on the modules labels and de scribes speed sort of t he mod ules, laten cies, access time from clock,SPD revision a nd Raw C ard version aco rding to the a ctua l JEDEC stand ard. 3.) Modules with stacked componen ts a re ava ila ble in two version , with componen ts stacke d using a soldering stacking tech niqu e (f.e. HYS72V1283 20GR-7 .5 ) and a n welding techniq ue developed by I NFINEON Te chn olog ies (f.e. HYS72V1283 21GR-7 .5) .
INFINE ON Technologies
2
2002-07-18
HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules
Pin Definitions and Functions
A0 - A11, A12 BA0, BA1 DQ0 - DQ6 3 Address In puts (A12 is u sed for 2 56Mbit based modules only) Bank Selects Da ta Inpu t/Output DQMB0 - DQMB7 CS0 - CS3 REGE*) Data Mask Chip Se lect Regist er Enab le "H" or N.C = registered mode "L" = buffe red mode Po wer (+ 3 .3 V) Gro und Clock for Presence Dete ct Se rial Data Out No Co nnection
CB0 - CB7 RAS CAS WE CKE0 CLK0 - CLK3
Ch eck Bits Ro w Add ress Strobe Co lumn Add re ss Strobe Re ad/Write Inp ut Clock Enable Clock In put
VDD VSS SC L SD A N.C.
Note : *) To co nfirm t o this specifica tion, mothe rbo ards must pull this p in to hig h st ate or no conn ect .
Address Format Density Organization Memory SDRAMs Banks 128 MB 16M × 72 128 MB 16M × 72 256 MB 32M x 72 256 MB 32M x 72 512 MB 64M × 72 1 GB 1 GB 2 GB 128M × 72 128M × 72 256M × 72 1 1 1 1 1 2 1 2 16M × 4 16M x 8 32M x 4 32M x 8 64M × 4 64M × 4 128M × 4 128M × 4 # of # of row /bank/ Refresh Period Interval SD RAMs columns bits 18 9 18 9 18 36 18 36 12/2/10 12/2/10 12/2/11 13/2/10 13/2/11 13/2/11 13/2/12 13/2/12 4k 4k 4k 8k 8k 8k 8k 8k 64 ms 15.6 µs 64 ms 15.6 µs 64 ms 15.6 µs 64 ms 7.8 µs 64 ms 7.8 µs 64 ms 7.8 µs 64ms 64ms 7.8 µs 7.8 µs
INFINE ON Technologies
3
2002-07-18
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