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Part: HYS72V32220GU-7.5-C2
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> 256 MB
Description: 128MB-1GB, 168pin
Company: Infineon Technologies Corporation
Datasheet: Download HYS72V32220GU-7.5-C2 datasheet File size : 2898 kB
Request For quote: Find where to buy HYS72V32220GU-7.5-C2
Datasheet text preview:
HYS 64/72V16300/32220GU SDRAM-Modules
3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules
· 168-Pin unbuffered 8-Byte Dual-In-Line SDRAM Modules for PC main memory applications · PC100-222, PC133-333 and PC133-222 versions · 1 bank 16M × 64, 16M × 72 and 2 bank 32M × 64, 32M × 72 organzation · Optimized for byte-write non-parity (x64) or ECC (x72) applications · JEDEC standard Synchronous DRAMs (SDRAM) · Fully PC board layout compatible to INTEL's Rev. 1.0 Module Specification · SDRA M Performance: -7 /-7.5 PC133
fCK Max. Clock
· Pr ogrammed Latencies: Pr oduct Speed -7 -7.5 -8 PC 133-222 PC 133-333 PC 100-222 CL 2 3 2
tR CD t RP
2 3 2
2 3 2
· Single +3.3 V( ±0.3 V) Power Supply · Pr ogrammable CAS Latency, Burst Length, and Wrap Sequence (S equential and Interleave) · Auto-Refresh (CBR) and Self-Refresh · Decoupling capacitors mounted on substrate · All inputs and outputs are LVTTL compatible · Serial Presence Detect with E2P ROM
-8 PC100 100 6
Unit MHz ns
133 5.4
· Utilizes 16M × 8 SDRAMs in TSOPII-54 packages with 4096 refresh cycles every 64 ms · 133.35 mm × 31.75 mm × 4,00 mm card size with gold-contact pads (JEDEC MO-161-BA)
Frequency
tAC Clock Access
Time
Description The HYS 64(72)V16300GU and HYS 64(72)V 32220GU are industry-standard 168-pin 8-byte Dual In-line Memory Modules (DIMMs) which are organized as 16M × 64, 16M × 72 in 1 bank and 32M × 64 and 32M × 72 in two banks of high-speed memory arrays designed with 128Mbit S ynchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -7 speed sor ted 16M × 8 SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, -7.5 speed sorted for PC133-333 and use -8 components for the standard PC100-222 applications. Decoupling capacitors are mounted on the PC board. The PC board design is in accordance with INTEL's Module Specification. The DIMMs have Serial Presence Detect, implemented with a serial E 2PROM using the two-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25" (31.75 mm) height.
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HYS 64/72V16300/32220GU SDRAM-Modules
Ordering Information Type 128 MByte DIMMs HYS 64V16300GU -7-C2 PC133-222-520 L-DIM-168- 33 133 Mhz 16M × 64 1 bank SDRAM module 1.25" 1.25" 1.25" 1.25" 1.25" 1.25" Code Package Descriptions Module Height
HYS 64V16300GU -7.5-C2 PC133-333-520 L-DIM-168- 33 133 Mhz 16M × 64 1 bank SDRAM module HYS 64V16300GU -8-C2 HYS 72V16300GU -7-C2 PC100-222-620 L-DIM-168- 33 100 MHz 16M × 64 1 bank SDRAM module PC133-222-520 L-DIM-168- 33 133 Mhz 16M × 72 1 bank SDRAM module
HYS 72V16300GU -7.5-C2 PC133-333-520 L-DIM-168- 33 133 Mhz 16M × 72 1 bank SDRAM module HYS 72V16300GU -8-C2 256 MByte DIMMs HYS 64V32220GU -7-C2 PC133-222-520 L-DIM-168- 30 133 MHz 32M × 64 2 bank SDRAM module PC100-222-620 L-DIM-168- 33 100 MHz 16M × 72 1 bank SDRAM module
1.25" 1.25" 1.25" 1.25" 1.25" 1.25"
HYS 64V32220GU -7.5-C2 PC133-333-520 L-DIM-168- 30 133 MHz 32M × 64 2 bank SDRAM module HYS 64V32220GU -8-C2 HYS 72V32220GU -7-C2 PC100-222-620 L-DIM-168- 30 100 MHz 32M × 64 2 bank SDRAM module PC133-222-520 L-DIM-168- 30 133 Mhz 32M × 72 2 bank SDRAM module
HYS 72V32220GU -7.5-C2 PC133-333-520 L-DIM-168- 30 133 Mhz 32M × 72 2 bank SDRAM module HYS 72V32220GU -8-C2 PC100-222-620 L-DIM-168- 30 100 Mhz 32M × 72 2 bank SDRAM module
Note: A ll part numbers end with a place code, designating the die revision. Consult factory for current revision. Example: HYS 64V16300GU-8-C2, indicates that Rev.C2 dies are used for S DRAM components.
INFINE ON Technologies
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HYS 64/72V16300/32220GU SDRAM-Modules
Pin Definitions and Functions A0-A11 BA0, BA1 CB0-CB7 RAS CAS Address Inputs Bank Selects Check Bits (x72 modules only) Column Address Strobe WE CK E0, CKE1 *) CLK0 - CLK3 Read/Write Input V SS Clock Enable Clock Input Ground
SCL Clock for SPD SDA Serial Data Out N.C . No Connection
DQ0 - DQ63 Data Input/Output
DQMB0 - DQMB7 Data Mask Chip Select Power (+3.3 V)
Row Address Strobe CS 0 - CS3 *)
VD D
*) CKE1, CS1 and CS3 on two bank modules only
Address Format Part Number 16M × 64 HYS 64V 16300GU 16M × 72 HYS 72V 16300GU 32M × 64 HYS 64V 32220GU 32M × 72 HYS 72V 32220GU Rows 12 12 12 12 Columns 10 10 10 10 Bank Select 2 2 2 2 Refresh Period Interval 4k 4k 4k 4k 64 ms 64 ms 64 ms 64 ms 15,6 µs 15,6 µs 15,6 µs 15,6 µs
Pin Configuration PIN# Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIN# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Symbol PIN# 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Symbol PIN# 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Symbol
V SS
DQ 0 DQ 1 DQ 2 DQ 3
V SS
DU CS2 DQMB2 DQMB3 DU
VS S
DQ 3 2 DQ 3 3 DQ 3 4 DQ 3 5
VS S
CKE 0 CS3 DQMB6 DQMB7 N.C.
V DD
DQ 4 DQ 5 DQ 6 DQ 7 DQ 8
VDD
DQ 3 6 DQ3 7 DQ3 8 DQ 3 9 DQ 4 0
V DD
N.C. N.C. N.C. (CB2) N.C. (CB3)
VDD
N.C. N.C. CB6 CB7
V SS
DQ 9 DQ 1 0 DQ 1 1
V SS
DQ 1 6 DQ 1 7 DQ 1 8
VS S
DQ 4 1 DQ 4 2 DQ 4 3
VS S
DQ 4 8 DQ 4 9 DQ 5 0
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