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Part: HYS72V32200GR-8
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
Description: 3.3v 168 Pin Registered Sdram Modules 64mb, 128mb, 256mb & 512mb Density
Company: Infineon Technologies Corporation
Datasheet: Download HYS72V32200GR-8 datasheet File size : 2898 kB
Request For quote: Find where to buy HYS72V32200GR-8
Datasheet text preview:
HY S 7 2V x2xxG R PC100 Registered SDRAM-Modules
3.3 V 168-pin Registered PC100 SDRAM Modules 64 MB, 128 MB, 256 MB, 512 MB & 1 GB Densities
· 168-pin JEDEC Standard, Registered 8 Byte Dual-In-Line SDRAM Module for PC and Server main memory applications · One bank 8M × 72, 16M × 72, 32M × 72 and 64M × 72 organization, two bank 128M × 72 organization · Optimized for ECC applications with very low input capacitances · Programmed Latencies: Product Speed -8 PC100 CL 2
t RC D tRP
· Auto Refresh (CBR) and Self Refresh · All inputs and outputs are LVTTL compatible · Serial Presence Detect with E2P ROM · Utilizes SDRAMs in TSOPII-54 packages with registers and PLL. The two bank module uses stacked TSOP54 packages. · Card Size: 133.35 mm × 38.1 mm/43.18 mm with Gold contact pads (JEDEC MO-161)
2
2
· Single + 3.3 V (± 0.3 V) power supply · Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) · Performance:
· This specification follows INTEL's "PC SDRAM Registered DIMM Specification" Rev. 1.2
-8 PC100
f CK t CK tAC
Unit M Hz ns ns
Clock Frequency (max.) Clock Cycle Time (min.) Clock Access Time (min.)
100 10 6
The HYS 72Vx2x0GR family are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 8M × 72, 16M × 72, 32M × 72, 64M × 72 & 128M × 72 high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. The 32M x 72 (256MByte) registered DIMM module is available in two versions (12 or 13 row addresses). All control and address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the P C board. The DIMMs use a serial presence detects scheme implemented via a serial E2P ROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint.
INFINEON Technologies
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HYS 72Vx2xxGR PC100 Registered SDRAM-Modules
Ordering Information Type HYS 72V8200GR-8-C HYS 72V8200GR-8-E HYS 72V16200GR -8-C HYS 72V16200GR -8-E HYS 72V16201GR -8-C2 HYS 72V32201GR -8-C2 HYS 72V32200GR -8-C2 HYS 72V64200GR -8-C2 Compliance Code Description SDRAM Technology 64 MBit (x8) 64 MBit (x4) 128 MBit (x8) 128 MBit (x4) 256 MBit (x8) 256 MBit (x4) 256 MBit (x4 stacked)
PC100-222-622R one bank 64 MB Reg. DIMM PC100-222-622R one bank 128 MB Reg. DIMM PC100-222-622R one bank 128 MB Reg. DIMM PC100-222-622R one bank 256 MB Reg. DIMM PC100-222-622R one bank 256 MB Reg. DIMM PC100-222-622R one bank 512 MB Reg. DIMM
HYS 72V128220GR-8-C2 PC100-222-622R two bank 1 GByte Reg. DIMM
Note: A ll part numbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS 64V8200GR-8-C2, indicating Rev. C2 dies are used for SDRAM components.
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HYS 72Vx2xxGR PC100 Registered SDRAM-Modules
Pin Definitions and Functions A0 - A11, A12 Address Inputs BA0, BA1 DQ0 - DQ63 Bank Selects Data Input/Output DQMB0 - DQMB7 Data Mask CS0 - CS3 REGE *) Chip Select Register Enable
"H" or N.C = registered mode "L" = buffered mode
CB0 - CB7 RAS CAS WE CKE0
Check Bits (x72 organization only) V D D Row Address Strobe Column Address Strobe Read/Write Input Clock Enable
P ower (+ 3.3 V ) Ground Clock for Presence Detect S erial Data Out No Connection
V SS
SCL SDA N.C.
CLK0 - CLK3 Clock Input
*) note : To confirm to this specification, motherboards must pull this pin to high state or no connect.
Address Format Density Organization Memory SDRAMs Banks 64 MB 8M × 72 1 1 1 1 1 1 2 8M × 8 16M × 4 16M x 8 32M × 4 32M × 8 64M × 4 64M × 4 128 MB 16M × 72 128 MB 16M × 72 256 MB 32M × 72 256 MB 32M × 72 512 MB 64M × 72 1 GB 128M × 72 # of # of row/bank/ Refresh Period Interval SD RAMs columns bits 9 18 9 18 9 18 36 12/2/9 12/2/10 12/2/10 12/2/11 13/2/10 13/2/11 13/2/11 4k 4k 4k 4k 8k 8k 8k 64 ms 15.6 µs 64 ms 15.6 µs 64 ms 15.6 µs 64 ms 15.6 µs 64 ms 7.8 µs 64 ms 7.8 µs 64 ms 7.8 µs
Pin Configuration P IN# Symbol 1 2 3 4 5 6 7 8 9 PIN# 43 44 45 46 47 48 49 50 51 Symbol PIN# 85 86 87 88 89 90 91 92 93 Symbol PIN# 127 128 129 130 131 132 133 134 135 Symbol
V SS
DQ 0 DQ 1 DQ 2 DQ 3
V SS
DU CS2 DQMB2 DQMB3 DU
VS S
DQ 3 2 DQ 3 3 DQ 3 4 DQ 3 5
VS S
CKE 0 CS3 DQMB6 DQMB7 N.C.
V DD
DQ 4 DQ 5 DQ 6
VDD
DQ 3 6 DQ3 7 DQ3 8
V DD
N.C. N.C.
VDD
N.C. N.C.
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