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Part: HYS64V16300GU-7
Category:
Description:
Company: Infineon Technologies Corporation
Datasheet: Download HYS64V16300GU-7 datasheet File size : 1224 kB
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HYS 64/72V16300/32220GU S DRAM-Modules
3.3 V 16M × 64/72-Bit 1 Bank SDRAM Module 3.3 V 32M × 64/72-Bit 2 Bank SDRAM Module 168-Pin Unbuffered DIMM Modules
· 168-Pin unbuffered 8-Byte Dual-In-Line SDRAM Modules for PC main memory applications · PC100-222, PC133-333 and PC133-222 versions · 1 bank 16M × 64, 16M × 72 and 2 bank 32M × 64, 32M × 72 organzation · Optimized for byte-write non-parity (x64) or ECC (x72) applications · JEDEC standard Synchronous DRAMs (SDRAM) · Fully PC board layout compatible to INTEL's Rev. 1.0 Module Specification · SDRAM Performance: -7 /-7.5 PC133
fCK Max. Clock
· Programmed Latencies: Product Speed -7 - 7.5 -8 PC133-222 PC133-333 PC100-222 CL 2 3 2
tRCD t RP
2 3 2
2 3 2
· Single +3.3 V(±0.3 V) Power Supply · Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential and Interleave) · Auto-Refresh (CBR) and Self-Refresh · Decoupling capacitors mounted on substrate · All inputs and outputs are LVTTL compatible · Serial Presence Detect with E2PROM
-8 PC100 100 6
Unit MHz ns
133 5.4
· Utilizes 16M × 8 SDRAMs in TSOPII-54 packages with 4096 refresh cycles every 64 ms · 133.35 mm × 31.75 mm × 4,00 mm card size with gold-contact pads (JEDEC MO-161-BA)
Frequency
tAC Clock Access
Time
The HYS 64(72)V16300GU and HYS 64(72)V32220GU are industry-standard 168-pin 8-byte Dual In-line Memory Modules (DIMMs) which are organized as 16M × 64, 16M × 72 in 1 bank and 32M × 64 and 32M × 72 in two banks of high-speed memory arrays designed with 128Mbit Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -7 speed sorted 16M × 8 SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, -7.5 speed sorted for PC133-333 and use -8 components for the standard PC100-222 applications. Decoupling capacitors are mounted on the PC board. The PC board design is in accordance with INTEL's PC SDRAM Rev. 1.0 Module Specification. The DIMMs have Serial Presence Detect, implemented with a serial E2PROM using the two-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 168pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25" (31.75 mm) height.
INFINEON Technologies
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HYS 64/72V16300/32220GU S DRAM-Modules
Ordering Information Type 128 MByte DIMMs HYS 64V16300GU-7-C2 PC133-222-520 L-DIM-168-33 133 Mhz 16M × 64 1 bank SDRAM module 1 .2 5 " 1 .2 5 " 1 .2 5 " 1 .2 5 " 1 .2 5 " 1 .2 5 " Code Package Descriptions Module Height
HYS 64V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M × 64 1 bank SDRAM module HYS 64V16300GU-8-C2 HYS 72V16300GU-7-C2 PC100-222-620 L-DIM-168-33 100 MHz 16M × 64 1 bank SDRAM module PC133-222-520 L-DIM-168-33 133 Mhz 16M × 72 1 bank SDRAM module
HYS 72V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M × 72 1 bank SDRAM module HYS 72V16300GU-8-C2 256 MByte DIMMs HYS 64V32220GU-7-C2 PC133-222-520 L-DIM-168-30 133 MHz 32M × 64 2 bank SDRAM module PC100-222-620 L-DIM-168-33 100 MHz 16M × 72 1 bank SDRAM module
1 .2 5 " 1 .2 5 " 1 .2 5 " 1 .2 5 " 1 .2 5 " 1 .2 5 "
HYS 64V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 MHz 32M × 64 2 bank SDRAM module HYS 64V32220GU-8-C2 HYS 72V32220GU-7-C2 PC100-222-620 L-DIM-168-30 100 MHz 32M × 64 2 bank SDRAM module PC133-222-520 L-DIM-168-30 133 Mhz 32M × 72 2 bank SDRAM module
HYS 72V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 Mhz 32M × 72 2 bank SDRAM module HYS 72V32220GU-8-C2 PC100-222-620 L-DIM-168-30 100 Mhz 32M × 72 2 bank SDRAM module
Note: All part numbers end with a place code, designating the die revision. Consult factory for current revision. Example: HYS 64V16300GU-8-C2, indicates that Rev.C2 dies are used for SDRAM components.
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HYS 64/72V16300/32220GU S DRAM-Modules
Pin Definitions and Functions A0-A11 BA0, BA1 CB 0- CB 7 RAS CAS Address Inputs Bank Selects Check Bits (x72 modules only) Column Address S tr o b e WE CKE0, CKE1 CLK0 - CLK3 Read/Write Input Clock Enable Clock Input
VSS Ground
SCL Clock for SPD SDA Serial Data Out N.C. No Connection
DQ0 - DQ63 Data Input/Output
DQMB0 - DQMB7 Data Mask Chip Select Power (+3.3 V)
Row Address Strobe CS0 - CS3
V DD
Address Format Part Number 16M × 64 HYS 64V16300GU 16M × 72 HYS 72V16300GU 32M × 64 HYS 64V32220GU 32M × 72 HYS 72V32220GU Rows 12 12 12 12 Columns 10 10 10 10 Bank Select 2 2 2 2 Refresh 4k 4k 4k 4k Period Interval 64 m s 64 m s 64 m s 64 m s 15,6 µ s 15,6 µ s 15,6 µ s 15,6 µ s
Pin Configuration PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol PIN# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Symbol PIN# 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 3 Symbol PIN# 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Symbol
VS S
DQ0 DQ1 DQ2 DQ3
VSS
DU CS 2 DQ MB 2 DQ MB 3 DU
VS S
DQ 32 DQ33 DQ34 DQ35
VSS
CK E 0 CS 3 DQ MB 6 DQ MB 7 N.C.
VD D
DQ4 DQ5 DQ6 DQ 7 DQ 8
VD D
DQ 36 DQ 37 DQ 38 DQ39 DQ40
V DD
N.C. N.C. N.C. (CB2) N.C. (CB3)
V DD
N.C. N.C. CB 6 CB 7
VS S
DQ 9 DQ 10 DQ 11 DQ 12
VSS
DQ16 DQ 17 DQ 18 DQ 19
VS S
DQ41 DQ 42 DQ 43 DQ 44
VSS
DQ 48 DQ 49 DQ 50 DQ 51 8 .00
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