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Part: HYS64D128320GU-6-A
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> 1 GB
Description: 128MB - 2GB, 184pin
Company: Infineon Technologies Corporation
Datasheet: Download HYS64D128320GU-6-A datasheet File size : 904 kB
Request For quote: Find where to buy HYS64D128320GU-6-A
Datasheet text preview:
HY S 64/ 72D64 000/ 128020G U-7/ 8-A Unbuffered DDR-I SDRAM-Modules
2.5 V 184-pin U nbuffered DDR-I SDRAM Modules 512 MByte & 1024 MByte Modules PC1600, PC2100 & PC2700 Preliminary datasheet rev. 0.8
· 184-pin Unbuffered 8-Byte Dual- In-Line DDR-I SDRAM non-par ity and E CC-Modules for PC and Server main memor y applications · One bank 64M x 64, 64M x 72 and two bank 128M x 64, 128M × 72 organization · JEDEC standar d Double Data Rate Synchronous DRAMs (DDR-I SDRAM) Single + 2.5 V (± 0.2 V) power supply · Built with 512 Mbit DDR-I SDRAMs organized as 64Mb x 8 in 66-Lead TSOPII package · Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) · Performance: -6 Component S peed Grade Module S peed Grade
fCK fCK
· Auto Refresh (CBR) and S elf Refresh · All inputs and outputs SSTL_2 compatible · Serial Presence Detect with E2P ROM · Jedec standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max. · Jedec standard reference layout · Gold plated contacts
-7 PC2100 143 133
-8 PC1600 125 100
Unit
DDR333B DDR266A DDR200 PC2700 166 133 M Hz M Hz
Clock Frequency (max.) @ CL = 2.5 Clock Frequency (max.) @ CL = 2
The H YS64/72D64000GU and HYS 64/72D128020GU are industry standard 184-pin 8-byte Dual in-line Memory Modules (D IMMs) organized as 64M × 64 and 128M × 64 for non-parity and 64M x 72 and 128M x 72 for ECC main memory applications. The memory ar ray is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PR OM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
1
2002-05-08 (rev.0.8)
HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Ordering Inf ormation
Type PC2 700 (CL=2.5): HYS64D12 8320GU-6-A HYS72D12 80320 GU-6-A PC2 100 (CL=2): HYS64D64 000GU-7-A HYS72D64 000GU-7-A HYS64D12 8020GU-7-A HYS72D12 8020GU-7-A PC1 600 (CL=2): HYS64D64 000GU-8-A HYS72D64 000GU-8-A HYS64D12 8020GU-8-A HYS72D12 8020GU-8-A No te: PC1600-20 220-A1 PC1600-20 220-A1 PC1600-20 220-B1 PC1600-20 220-B1 on e bank 512 MB DIMM on e bank 512 MB ECC-DIMM two banks 1 024 MB DIMM two banks 1 024 MB ECC-DIMM 5 12 MBit 5 12 Mbit 5 12 MBit 5 12 MBit PC2100-20 330-A1 PC2100-20 330-A1 PC2100-20 330-B1 PC2100-20 330-B1 on e bank 512 MB DIMM on e bank 512 MB ECC-DIMM two banks 1 024 MB DIMM two banks 1 024 MB ECC-DIMM 5 12 MBit 5 12 Mbit 5 12 MBit 5 12 MBit PC2100-25 330-B1 PC2100-25 330-B1 two banks 1 024 MB DIMM two banks 1 024 MB ECC-DIMM 5 12 MBit 5 12 MBit Compliance Code Des cription S DRAM Technology
All part numb ers end with a p lace cod e, designa ting th e silicon-die revision. Reference inf ormatio n available on re quest. Example : HYS 72D64 000GU-8-A, indicating Rev.A dies are used for the SDRAM co mpone nts. The Compliance Code is printe d on th e mod ule labe ls and d escribes the spe ed sort fe. "PC2 100", the la tencies (f.e. "203 30" mean s CAS latency = 2, trcd lat ency = 3 and trp laten cy =3 ) and the Ra w Card used for this module.
INFINE ON Technologies
2
2002-05-08 (rev.0.8)
HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A1 2 BA0, BA1 DQ0 - DQ63 CB0 - CB7 RA S CA S WE CKE0 - CKE1 DQS0 - DQS8 CL K0 - CLK2, CL K0 - CLK2 DM0 - DM8 DQS9 - DQS17 Address Inpu ts Bank Selects Data Input/ Outp ut Check Bits (x72 organ izatio n only) Row Address Strobe Column Address Strobe Read /Writ e Input Clock En able SDRAM low dat a st rob es SDRAM clo ck (p ositive line s) SDRAM clo ck (n egative lines) SDRAM low dat a mask/ high da ta stro bes S0, S1 VDD VSS VDDQ VDDI D VREF VDDSPD SCL SDA SA0 - SA2 NC Chip Se lects Po wer (+ 2 .5 V) Gro und I/O Driver power supply VDD Indentification flag I/O reference supply Se rial EEPROM power supply Se rial b us clock Se rial b us data line slave add ress select no conn ect
note: S1 and CKE1 are used on two bank modules only
Address Format
Density 512 MB 512 MB Orga nization 64M x 64 64M x 72 Memo ry Ban ks 1 1 2 2 SDRAMs 64M x 8 64M x 8 64M x 8 64M x 8 # of SDRAMs 8 9 16 18 # o f ro w/bank/ columns bits 13/ 2/11 13/ 2/11 13/ 2/11 13/ 2/11 Refresh 8k 8k 8k 8k Period 64 ms 64 ms 64 ms 64 ms I nterval 7 .8 µs 7 .8 µs 7 .8 µs 7 .8 µs
1024 MB 128M × 64 1024 MB 128M × 72
INFINE ON Technologies
3
2002-05-08 (rev.0.8)
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