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Part: HYB514100BJ-50
Category:
Description: 4M X 1bit DRAM
Company: Infineon Technologies Corporation
Datasheet: Download HYB514100BJ-50 datasheet File size : 391 kB
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Datasheet text preview:
4M × 1-Bit Dynamic RAM
HYB 514100BJ-50/-60
Advanced Information · 4 194 304 words by 1-bit organization · 0 to 70 °C operating temperature · Fast Page Mode Operation · Performance: -50 -60 60 15 30 110 40 ns ns ns ns ns
tRAC RAS access time tCAC CAS access time tAA tRC tPC
Access time from address Read/Write cycle time Fast page mode cycle time
50 13 25 95 35
· Single + 5 V (± 10 %) supply with a built-in VBB generator · Low power dissipation max. 660 mW active (-50 version) max. 605 mW active (-60 version) · Standby power dissipation: 11 mW max. standby (TTL) 5.5 mW max. standby (CMOS) · Output unlatched at cycle end allows two-dimensional chip selection · Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability · All inputs and outputs TTL-compatible · 1024 refresh cycles/16 ms · Plastic Packages: P-SOJ-26/20-2 with 300 mil width
Semiconductor Group
1
1998-10-01
HYB 514100BJ-50/-60 4M × 1 DRAM
The HYB 514100BJ is the new generation dynamic RAM organized as 4 194 304 words by 1-bit. The HYB 514100BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514100BJ to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Type HYB 514100BJ-50 HYB 514100BJ-60 Ordering Code Q67100-Q971 Q67100-Q759 Package P-SOJ-26/20-2 300 mil P-SOJ-26/20-2 300 mil Descriptions DRAM (access time 50 ns) DRAM (access time 60 ns)
P-SOJ-26/20-2
V SS DO CAS N.C. A9
DI WE RAS N.C. A10
1 2 3 4 5
26 25 24 23 22
A0 A1 A2 A3 V CC
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
SPP02808
Pin Configuration Pin Names A0 A10 RAS CAS WE DI DO Address Input Row Address Strobe Column Address Strobe Read/Write Input Data In Data Out Power Supply (+ 5 V) Ground (0 V) No Connection
VCC VSS
N.C.
Semiconductor Group
2
1998-10-01
HYB 514100BJ-50/-60 4M × 1 DRAM
WE CAS
&
Data In Buffer
DI
No.2 Clock Generator
Data Out Buffer
DO
11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 11
Column Address Buffers (11)
11 Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
Refresh Counter (10) 10 Row Address Buffers (11) 10 Row Decoder . . . 1024 . . .
4096
Memory Array
. . .
. . .
RAS
No.1 Clock Generator Substrate Bias Generator
V CC V SS
SPB02847
Block Diagram
Semiconductor Group
3
1998-10-01
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