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Part: HYB39S512800AT-7
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 512 Mb
Description: 512Mbit Synchronous DRAMs
Company: Infineon Technologies Corporation
Datasheet: Download HYB39S512800AT-7 datasheet File size : 782 kB
Request For quote: Find where to buy HYB39S512800AT-7
Datasheet text preview:
HYB39S512400/800/160AT(L) 512MBit Synchronous DRAM
512 MBit Synchronous DRAM
Preliminary Datasheet April '01
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High Performance:
-6 fCK tCK3 tAC3 tCK2 tAC2 166 6 5 7.5 5.4 -7 1 43 7 5 .4 7 .5 5 .4 -7.5 133 7.5 5.4 10 6 -8 125 8 6 10 6 Units MHz ns ns ns ns
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Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge
Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) A uto Refresh (CBR) and Self Refresh P ower Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7,8 µs) Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface versions P lastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) - 6 parts for PC166 3-3-3 operation - 7 parts for PC133 2-2-2 operation - 7.5 parts for PC133 3-3-3 operation - 8 parts for PC100 2-2-2 operation
· · · · · ·
Fully Synchronous to Positive Clock Edge 0 to 70 °C operating temperature Four Banks controlled by BA0 & BA1 P rogrammable CAS Latency: 2 & 3 P rogrammable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page
The HYB39S512400/800/160AT(L) are four bank Synchronous DRAM's organized as 4 banks x 32MBit x4, 4 banks x 16MBit x8 and 4 banks x 8Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that pr efetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON's advanced 0.14 µm 512MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3V +/- 0.3V power supply. All 512Mbit components are housed in TSOPII-54 packages.
INFINEON Technologies
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HYB39S512400/800/160AT(L) 512MBit Synchronous DRAM
Ordering Information
Type Speed Grade Package Descri ption
HYB 39S512400AT-6 HYB 39S512400AT-7 HYB 39S512400AT-7.5 HYB 39S512400AT-8 HYB 39S512800AT-6 HYB 39S512800AT-7 HYB 39S512800AT-7.5 HYB 39S512800AT-8 HYB 39S512160AT-6 HYB 39S512160AT-7 HYB 39S512160AT-7.5 HYB 39S512160AT-8 HYB39S512xx0ATL
PC166 -33 3-520 PC133 -22 2-520 PC133 -33 3-520 PC100 -22 2-620 PC166 -33 3-520 PC133 -22 2-520 PC133 -33 3-520 PC100 -22 2-620 PC166 -33 3-520 PC133 -22 2-520 PC133 -33 3-520 PC100 -22 2-620 PC100 -xxx-620
P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil) P-TSOP-54 -2 (400mil)
166MHz 4B x 32M x 4 SDRAM 143MHz 4B x 32M x 4 SDRAM 133MHz 4B x 32M x 4 SDRAM 125MHz 4B x 32M x 4 SDRAM 166MHz 4B x 16M x 8 SDRAM 143MHz 4B x 16M x 8 SDRAM 133MHz 4B x 16M x 8 SDRAM 125MHz 4B x 16M x 8 SDRAM 166MHz 4B x 8M x 16 SDRAM 143MHz 4B x 8M x 16 SDRAM 133MHz 4B x 8M x 16 SDRAM 125MHz 4B x 8M x 16 SDRAM Low Power Versions (on request)
Pin Description
CLK CKE CS RAS CAS WE A0-A12 BA0, BA1 Clock Input Clock Enable Chip Select Row Address Strobe Colu mn Address Strobe Write Enable Address Inputs Ban k Select DQx DQM, LDQM, UDQM VDD VSS VDDQ VSSQ NC Data Input /Output Data Mask Power (+3.3V) Ground Power for DQ's (+ 3.3V) Ground for DQ's not connected
INFINEON Technologies
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HYB39S512400/800/160AT(L) 512MBit Synchronous DRAM
Pinout s:
32M x 16 64M x 8 128M x 4
VDD DQ0 VDDQ DQ1 DQ2 VSS Q DQ3 DQ4 VDDQ DQ5 DQ6 VSS Q DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD VDD D Q 0 NC VDDQ VDDQ NC NC DQ1 DQ0 VSSQ VSSQ NC NC D Q 2 NC VDDQ VDDQ NC NC DQ3 DQ1 VSSQ VSSQ NC NC VDD VDD NC NC WE WE CAS CAS RAS RAS CS CS BA0 BA0 BA1 BA1 A10/APA10/AP A0 A0 A1 A1 A2 A2 A3 A3 VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CL K CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS D Q15 VSSQ D Q14 D Q13 V DDQ D Q12 D Q11 VSSQ D Q10 D Q9 V DDQ D Q8 VSS NC U DQ M C LK C KE A12 A11 A9 A8 A7 A6 A5 A4 VSS
TS OPII-54 (400 mil x 875 mil, 0.8 mm pitch)
Pinout for x4, x8 & x16 organised 512M-DRAMs
INFINEON Technologies
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Others parts begin by hy
HY-1 HY-2 HY-3 HY-4 HY-5 HY-6 HY-7 HY-8 HY-9 HY-10 HY-11 HY-12 HY-13 HY-14 HY-15 HY-16 HY-17 HY-18 HY-19 HY-20 HY-21 HY-22 HY-23 HY-24 HY-25 HY-26 HY-27 HY-28 HY-29 HY-30 HY-31 HY-32 HY-33 HY-34
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