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Part: HYB39S256800DC-7
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 256 Mb
Description: 256Mbit Synchronous DRAMs
Company: Infineon Technologies Corporation
Datasheet: Download HYB39S256800DC-7 datasheet File size : 782 kB
Request For quote: Find where to buy HYB39S256800DC-7
Datasheet text preview:
HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM
256 MBit Synchronous DRAM
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High Performance:
-6 fCK tCK3 tAC3 tCK2 tAC2 166 6 5 7.5 5.4 -7 1 43 7 5 .4 7 .5 5 .4 -7.5 133 7.5 5.4 10 6 -8 125 8 6 10 6 Units MHz ns ns ns
· · · · · · · ns · · · ·
Data Mask for Read / Write contr ol (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR ) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7,8 µs) Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Inter face versions Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) Chipsize Packages: 54 ball TFBGA (12 mm x 8 mm) - 6 parts for PC166 3-3-3 oper ation - 7 parts for PC133 2-2-2 oper ation - 7.5 parts for PC133 3- 3-3 operation - 8 parts for PC100 2-2-2 oper ation
· · · · · · · ·
Fully Synchronous to Positive Clock Edge 0 to 70 °C operating temperatur e Four Banks controlled by BA 0 & BA1 P rogrammable CAS Latency: 2 & 3 P rogrammable Wrap Sequence: Sequential or Interleave P rogrammable Burst Length: 1, 2, 4, 8 and full page Multiple Burst Read with Single Write Operation A utomatic Command and C ontrolled Prechar ge
The HYB 39S256400/800/160DT(L) are four bank Synchronous DRAM's organized as 4 banks x 16MBit x4, 4 banks x 8MB it x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that pr efetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated w ith INFINEON's advanced 0.14 µm 256MBit DRAM process technology. The device is designed to comply with all industr y standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized w ith the positive edge of an exter nally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CB R) and Self Refresh operation are supported. These devices operate with a single 3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54 packages.
INFINEON Technologies
1
2002-04-23
HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM
Ordering Inf ormation
Type Speed Grade Package Descri ption
HYB 39S25640 0DT-6 HYB 39S25640 0DT-7 HYB 39S25640 0DT-7 .5 HYB 39S25640 0DT-8 HYB 39S25680 0DT-6 HYB 39S25680 0DT-7 HYB 39S25680 0DT-7 .5 HYB 39S25680 0DT-8 HYB 39S25616 0DT-6 HYB 39S25616 0DT-7 HYB 39S25616 0DT-7 .5 HYB 39S25616 0DT-8 HYB39S25680 0DTL-x HYB39S25616 0DTL-x HYB39S256xx0D C(L)-x
PC166 -33 3-520 PC133 -22 2-520 PC133 -33 3-520 PC100 -22 2-620 PC166 -33 3-520 PC133 -22 2-520 PC133 -33 3-520 PC100 -22 2-620 PC166 -33 3-520 PC133 -22 2-520 PC133 -33 3-520 PC100 -22 2-620
P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TSOP-54 -2 (4 00mil) P-TFBGA-54
166MHz 4B x 1 6M x 4 SDRAM 143MHz 4B x 1 6M x 4 SDRAM 133MHz 4B x 1 6M x 4 SDRAM 125MHz 4B x 1 6M x 4 SDRAM 166MHz 4B x 8 M x 8 SDRAM 143MHz 4B x 8 M x 8 SDRAM 133MHz 4B x 8 M x 8 SDRAM 125MHz 4B x 8 M x 8 SDRAM 166MHz 4B x 4 M x 16 SDRAM 143MHz 4B x 4 M x 16 SDRAM 133MHz 4B x 4 M x 16 SDRAM 125MHz 4B x 4 M x 16 SDRAM 4B x 8M x 8 SDRAM Low Power Versions (on reque st) 4B x 4M x 16 SDRAM Lo w Power Versions (on reque st) (on re quest)
Pin Description:
CLK CKE CS RAS CAS WE A0 -A12 BA0, BA1 Clock Input Clock Enab le Chip Se lect Row Ad dress Strobe Colu mn Address Strobe Write En able Address Inputs Ban k Sele ct DQx DQM, LDQM, UDQM VDD VSS VDDQ VSSQ NC Data I nput /Outp ut Data Mask Power (+3.3V) Ground Power for DQ's (+ 3.3 V) Ground for DQ's not connected
INFINEON Technologies
2
2002-04-23
HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM
Pinout s (TSOP-54)
16 M x 16 32 M x 8 64 M x 4
VDD
DQ0
VDD
DQ0
VDD
N.C.
VDDQ
DQ1 DQ2
VDDQ
N.C. DQ1
VDDQ
N.C. DQ0
VSSQ
DQ3 DQ4
VSSQ
N.C. DQ2
VSSQ
N.C. N.C.
VDDQ
DQ5 DQ6
VDDQ
N.C. DQ3
VDDQ
N.C. DQ1
VSSQ
DQ7
VSSQ
N.C.
VSSQ
N.C.
VDD
LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3
VDD
N.C. WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3
VDD
N.C. WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3
VDD
VDD
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS
N.C.
VSS
DQ7
VSS
DQ15
VSSQ
N.C. DQ3
VSSQ
N.C. DQ6
VSSQ
DQ14 DQ13
VDDQ
N.C. N.C.
VDDQ
N.C. DQ5
VDDQ
DQ12 DQ11
VSSQ
N.C. DQ2
VSSQ
N.C. DQ4
VSSQ
DQ10 DQ9
VDDQ
N.C.
VDDQ
N.C.
VDDQ
DQ8
VSS
N.C. DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4
VSS
N.C. DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4
VSS
N.C. UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4
VSS
VSS
VSS
TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)
SPP04126
INFINEON Technologies
3
2002-04-23
Others parts begin by hy
HY-1 HY-2 HY-3 HY-4 HY-5 HY-6 HY-7 HY-8 HY-9 HY-10 HY-11 HY-12 HY-13 HY-14 HY-15 HY-16 HY-17 HY-18 HY-19 HY-20 HY-21 HY-22 HY-23 HY-24 HY-25 HY-26 HY-27 HY-28 HY-29 HY-30 HY-31 HY-32 HY-33 HY-34
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