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Part: HYB3117800BSJ-50
Category:
Description: 2M X 8bit DRAM
Company: Infineon Technologies Corporation
Datasheet: Download HYB3117800BSJ-50 datasheet File size : 1211 kB
Request For quote: Find where to buy HYB3117800BSJ-50
Datasheet text preview:
2M × 8 - Bit Dynamic RAM 2k Refresh (Fast Page Mode)
Advanced Information · 2 097 152 words by 8-bit organization · 0 to 70 °C operating temperature · Fast Page Mode operation · Performance: -50 -60 60 15 30 104 40 ns ns ns ns ns
HYB 5117800/BSJ-50/-60 HYB 3117800BSJ-50/-60
tRAC tCAC tAA tRC tPC
RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time
50 13 25 84 35
· Power dissipation: HYB5117800 -50 Power Supply Active TTL Standby CMOS Standby 440 -60 5 ± 10% 385 11 5.5 HYB3117800 -50 288 -60 3.3 ± 0.3 V 252 7.2 3.6 mW mW mW
· Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode · All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible · 2048 refresh cycles / 32 ms (2k-refresh) · Plastic Package: P-SOJ-28-3 400 mil
Semiconductor Group
1
1998-10-01
HYB 5(3)117800/BSJ-50/-60 2M × 8 DRAM
The HYB 5(3)117800 are 16 MBit dynamic RAMs based on the die revisions "G" & "F" and organized as 2 097 152 words by 8-bits. The HYB 5(3)117800 utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)117800 to be packaged in a standard SOJ-28 plastic package. Package with 400 mil width are available. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. Ordering Information Type HYB 5117800BSJ-50 HYB 5117800BSJ-60 HYB 3117800BSJ-50 HYB 3117800BSJ-60 Ordering Code Q67100-Q1092 Q67100-Q1093 on request on request Package Descriptions
P-SOJ-28-3 400 mil 5 V 50 ns FPM-DRAM P-SOJ-28-3 400 mil 5 V 60 ns FPM-DRAM P-SOJ-28-3 400 mil 3.3 V 50 ns FPM-DRAM P-SOJ-28-3 400 mil 3.3 V 60 ns FPM-DRAM P-SOJ-28 400 mil
V CC I/O1 I/O2 I/O3 I/O4 WE RAS N.C. A10 A0 A1 A2 A3 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 V SS 27 I/O8 26 I/O7 25 I/O6 24 I/O5 23 CAS 22 OE 21 A9 20 A8 19 A7 18 A6 17 A5 16 A4 15 V SS
SPP02803
Pin Names and Configuration A0 - A10 A0 - A9 RAS OE I/O1 - I/O8 CAS WE Row Address Inputs Column Address Inputs Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply + 5 V for HYB 5117800 + 3.3 V for HYB 3117800 Ground (0 V) Not Connected
VCC
VSS
N.C.
Semiconductor Group
2
1998-10-01
HYB 5(3)117800/BSJ-50/-60 2M × 8 DRAM
I/O1 I/O2
I/O8
Data IN Buffer WE CAS 8 No.2 Clock Generator
&
Data OUT Buffer
OE
8
10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
Column Address Buffers (10)
10 Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
4
Refresh Counter (11) 11 11 Row Address Buffers (11) 11 Row Decoder 2048
1024 x8
Memory Array 2048 x 1024 x 8
RAS
No.1 Clock Generator Voltage Down Generator
SPB03456
VCC VCC (internal)
Block Diagram
Semiconductor Group
3
1998-10-01
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