|
|
Part: HYB25D256800BT
Category:
Memory
-> DRAM
-> DDR SDRAM
Description: 256mbit Double Data Rata Sdram
Company: Infineon Technologies Corporation
Datasheet: Download HYB25D256800BT datasheet File size : 4947 kB
Request For quote: Find where to buy HYB25D256800BT
Datasheet text preview:
HYB25D256[800/160]BT(L)-[5/5A] 256 MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9
Features
CAS Latency and Clock Frequency
CAS Latency 2 2. 5 3 Maximum Operating Frequency (MHz) DDR400B DD R400A -5 - 5A 133 133 166 200 200 200
· Double data rate architecture: two data transfers per clock cycle · Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver · DQS is edge-aligned with data for reads and is center-aligned with data for writes · Differential clock inputs (CK and CK) · Four internal banks for concurrent operation
· Data mask (DM) for write data · DLL aligns DQ and DQS transitions with CK transitions · Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS · Burst Lengths: 2, 4, or 8 · CAS Latency: (1.5), 2, 2.5, (3) · Auto Precharge option for each burst access · Auto Refresh and Self Refresh Modes · 7.8ms Maximum Average Periodic Refresh Interval (8k refresh) · 2.5V (SSTL_2 compatible) I/O · VDDQ = 2.6V ± 0.1V / VDD = 2.6V ± 0.1V · TSOP66 package
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coinci2003-01-10, V0.9
dent with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
Page 1 of 29
HYB25D256[800/160]BT(L)-[5/5A] 256 MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Ordering Information
Par t Numbera O rg . CAS-RCD-RP Clock CAS-RCD-RP Clock CAS-RCD-RP Clock Speed Latencies (MHz) Latencies (MHz) Latencies (M Hz) 3-3-3 2 00 2.5 - 3 - 3 200 2-3-3 133 Package
HYB25D256800BT(L)-5A x 8 HYB25D256160BT(L)-5A x 16 HYB25D256800BT(L)-5 HYB25D256160BT(L)-5 x8 x 16
DDR400A 66 Pin TSOP-II
166
DDR400B
a. HYB: designator for memory components 25D: DDR-I SDRAMs at Vddq=2.5V 256: 256Mb density 400/800/160: Product variations x4, x8 and x16 B: Die revision B C/T: Package type FBGA and TSOP L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents -5: speed grade - see table
Page 2 of 29
2003-01-10, V0.9
HYB25D256[800/160]BT(L)-[5/5A] 256 MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Pin Configuration (TSOP66)
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC WE CA S RA S CS NC BA0 BA1 A10/ AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ NC DQ1 V SSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 A10/ AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ DQ1 DQ2 V SS Q DQ3 DQ4 VDDQ DQ5 DQ6 V SS Q DQ7 NC VDDQ LDQ S NC VDD NC LDM WE CA S RA S CS NC BA0 BA1 A10/ AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 16Mb x 16 32Mb x 8 64Mb x 4
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 V SS
V SS DQ7 V SSQ NC DQ6 VDDQ NC DQ5 V SSQ NC DQ4 VDDQ NC NC V SSQ DQS NC V R EF V SS DM CK CK CK E NC A 12 A 11 A9 A8 A7 A6 A5 A4 VSS
V SS NC V SSQ NC DQ3 VDDQ NC NC V SSQ NC DQ2 VDDQ NC NC V SSQ DQS NC V R EF V SS DM CK CK CK E NC A 12 A 11 A9 A8 A7 A6 A5 A4 V SS
2003-01-10, V0.9
Page 3 of 29
Others parts begin by hy
HY-1 HY-2 HY-3 HY-4 HY-5 HY-6 HY-7 HY-8 HY-9 HY-10 HY-11 HY-12 HY-13 HY-14 HY-15 HY-16 HY-17 HY-18 HY-19 HY-20 HY-21 HY-22 HY-23 HY-24 HY-25 HY-26 HY-27 HY-28 HY-29 HY-30 HY-31 HY-32 HY-33 HY-34
|
|
|
