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Part: HYB25D256400AT-8
Category:
Memory
-> DRAM
-> DDR SDRAM
-> 256 Mb
Description:
Company: Infineon Technologies Corporation
Datasheet: Download HYB25D256400AT-8 datasheet File size : 1705 kB
Request For quote: Find where to buy HYB25D256400AT-8
Datasheet text preview:
HYB25D256400/800AT 256-MBit Double Data Rata SDRAM
Features
CAS Latency and Frequency
CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR266A DDR200 -7 -8 133 100 143 125
· Double data rate architecture: two data transfers per clock cycle · Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver · DQS is edge-aligned with data for reads and is center-aligned with data for writes · Differential clock inputs (CK and CK) · Four internal banks for concurrent operation
· Data mask (DM) for write data · DLL aligns DQ and DQS transitions with CK transitions. · Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS · Burst lengths: 2, 4, or 8 · CAS Latency: 2, 2.5 · Auto Precharge option for each burst access · Auto Refresh and Self Refresh Modes · 7.8 µs Maximum Average Periodic Refresh Interval · 2.5V (SSTL_2 compatible) I/O · VDDQ = 2.5V ± 0.2V / VDD = 2.5V ± 0.2V · TSOP66 package
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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HYB25D256400/800AT 256-Mbit Double Data Rate SDRAM
Pin Configuration
VDD NC VDDQ NC DQ 0 VSSQ NC NC VDDQ NC DQ 1 VSSQ NC NC VDDQ NC NC VDD NU NC WE CA S RA S CS NC BA0 BA1 A10 /AP A0 A1 A2 A3 VDD VDD DQ 0 VDDQ NC DQ 1 VSSQ NC DQ 2 VDDQ NC DQ 3 VSSQ NC NC VDDQ NC NC V DD NU NC WE CA S RA S CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ 7 VSSQ NC DQ 6 V DDQ NC DQ 5 VSSQ NC DQ 4 V DDQ NC NC VSSQ DQ S NC V RE F VSS DM* CK CK CKE NC A1 2 A1 1 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ 3 VDDQ NC NC VSSQ NC DQ 2 VDDQ NC NC VSSQ DQ S NC VREF VSS DM * CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
6 6-p in Plastic TSOP-II 400mil
32Mb x 8 64Mb x 4 I
Column Address Table Organization 64Mb x 4 32Mb x 8 Column Address A 0-A9, A11 A0-A9
* DM is internally loaded to match DQ and DQS identically.
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HYB25D256400/800AT 256-Mbit Double Data Rate SDRAM
Input/Output Functional Description
Symbol CK, CK Type Input Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. No Connect: No internal electrical connection is present. Don't use Supply Supply Supply Supply Supply DQ Power Supply: 2.5V ± 0.2V. DQ Ground Power Supply: 2.5V ± 0.2V. Ground S STL_2 reference voltage: (V D DQ / 2)
CKE
Input
CS RAS, CAS, WE
Input Input
DM
Input
BA 0, BA1
Input
A0 - A12
Input
DQ DQ S NC NU VDDQ V SSQ VDD V SS VREF
Input/Output Input/Output
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