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Part: M2006
Category:
Timing Circuits
-> Frequency Translation
Description: Frequencytranslation PLL
Company: Integrated Circuit System
Datasheet: Download M2006 datasheet File size : 58 kB
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Micro Networks
An Integrated Circuit Systems Company
M2006-01
Preliminary Specifications
M2006-01
Frequency Synthesizer
DESCRIPTION
The M2006-01 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Synthesizer in a 9mm x 9mm surface mount package. The internal high "Q" SAW filter provides low jitter signal performance and determines the output frequency of the VCSO. Selecting between two differential LVPECL clocks or one single-ended LVCMOS / LVTTL clock provides the input reference signal to the Frequency Translator. The maximum input frequency is 700MHz. The M2006-01 will default to a multiplying factor of 32 on power-up. The multiplying factor can be changed by serially programming the input and feedback dividers via the configuration logic. A differential LVPECL signal provides the output clock for the device. A second differential output which can be programmed to divide the output frequency by a factor of 4 is also available. The output frequency can be momentarily increased or decreased to add or subtract one net output clock cycle by asserting the ADD_CLK or DROP_CLK inputs, respectively. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. A phase slope limiting feature, which reduces phase build-out in order to meet GR-253 MTIE upon an input transient, can be manually selected by asserting the PSL input. The phase slope limiting feature is automatically activated whenever a new input reference clock is selected. The frequency agility, bandwidth control, and phase slope limiting features make the M2006-01 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in OC-3 through OC-192 applications.
FEATURES
Output Clock Frequency up to 700MHz Intrinsic Jitter <1ps rms (12kHz - 50MHz) Automatic Phase Slope Limiting Dual Differential Inputs Input Compatible with LVPECL, LVDS, HSTL, SSTL, etc. Triple Input MUX Configurable Input and Feedback Dividers Tunable Loop Filter Response Two Differential LVPECL outputs Single 3.3V Supply Small 9mm x 9mm SMT Package
APPLICATIONS
ABSOLUTE MAX RATINGS Inputs, VI : ....... -0.5 to VCC+0.5V Output, VO : ....... -0.5 to VCC+0.5V Supply Voltage, VCC : ......... 4.6 V Storage Temperature, TSTO : .... -45°C to +100°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
SONET / SDH / 10GbE System Synchronization Add / Drop Muxes, Access and Edge Switches Line Card System Clock Cleaner / Translator Optical Module Clock Cleaner / Translator
Micro Networks 324 Clark Street Worcester, MA 01606
ISO 9001 Registered
tel: 508-852-5400
1
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL BLOCK DIAGRAM The internal PLL will adjust the VCSO output frequency to be M (feedback divider) divided by R (input divider) times the selected input reference clock frequency. Note that the ratio of M/R times input frequency must be such that it falls within the "lock" range of the VCSO. The M divider (10-bits) can be programmed for a maximum value of 1023 and a minimum value of 4. The R divider (9-bits) can be set to a maximum value of 511 and a minimum value of 1. There are two differential LVPECL outputs (Fout 0, Fout 1) which operate at the VCSO frequency. When P1 is HIGH the Fout 1 output will operate at 1/4 the VCSO frequency and when P1 is LOW Fout 1 output operates at the VCSO frequency. The relationship between the VCSO frequency, the M and R dividers, and the input REF_CLK is defined as follows: F VCSO = F REF_CLK x M / R On power-up the R and M dividers are set to 1 and 32, respectively. The input reference clock is selected from DIF_CLK 0, DIF_CLK 1, or REF_CLK by selecting the appropriate REF_SEL 0 and REF_SEL 1 inputs. When a new reference is selected the M2006-01 will automatically
R LOOP CLOOP
M2006-01
Preliminary Specifications
switch to the "phase slope limiting" mode to control the phase build-out of the output clocks. The ADD_CLK and DROP_CLK inputs increments or decrements the M (feedback) divider for one phase detector cycle. This results in a momentary increase or decrease in output frequency and an extra or missing output clock cycle relative to the input reference clock. The "phase slope limiter" is used to ensure MTIE compliance. The PSL input provides manual control.
When PSL is HIGH, the output phase slope is limited by changing the phase detector gain to a non-linear function. . The M2006-01 is serially programmed via a 3 wire interface. Refer to the timing diagram below (labeled "SERIAL PROGRAMMING") for the following explanation. Serial operation begins at point "(a)", when S_LOAD is LOW; the shift register is loaded one bit at-a-time by sampling the S_DATA bits with the rising edge of S_CLOCK. Divider load occurs at point "(b)" , when S_LOAD transitions Lfrom LOW to HIGH; all of the data in the shift register is loaded into the R and M dividers. atch occurs at point "(c)", on the HIGH-to-LOW transition of S_LOAD; divider values will not be affected by serial input. (If S_LOAD is held HIGH, any S_DATA input is passed directly to the R and M dividers on each rising edge of S_CLOCK.)
RPOST CPOST CPOST
Exte rnal Loop Filter Components
R LOOP
CLOOP OP_OUT
RPOST nOP_OUT nV C VC
M2006-01
MUX
OP_IN Phase Detector
nOP_IN
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_CLK REF_SEL1:0 2
RIN
SAW Delay Line
00
R Divider
R = 1-511 Power-Up Default = 1 RIN
01 1X
Loop Filter Amplifier
Phase Shifter
VCSO
M Divider
M = 3-1024 Power-Up Default = 32
S_DATA S_CLOCK S_LOAD
FOUT0 nFOUT0 P Divider
P = 1 ( P1 = 0 ) or 4 ( P1 = 1 )
Serial Configuration Register
FOUT1 nFOUT1
PSL
ADD_CLK
DROP_CLK
P1
SERIAL PROGRAMMING
S_DATA T2 T1 T0 R8 R7 R6 R5 R4 R3 R2 R1 R0 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
S_CLOCK
S_LOAD
(a) (b) (c)
Note: T1 and T0, which are used for test automation, must be set to 0. T2 is set to 1 for normal bandwidth, 0 for narrow bandwidth.
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
2
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL DESCRIPTION LOOP FILTER FIGURE 2
Rloop Cloop
M2006-01
Preliminary Specifications
The M2006-01 requires the use of an external loop filter via the provided filter pins. Due to the differential design, the implementation requires two identical RC filters as shown in Figure 2.
Rpost Cpost
Cpost Rloop Cloop Rpost
TABLE 1. EXAMPLE OF LOOP FILTER VALUES PLL Bandwidth 330Hz Damping Factor 2.0 R loop C loop R post C post
3.9K 12K 24K
2.2µF .22µF .1µF
20k 20k 20k
250pF 250pF 250pF
1015Hz 1975Hz
2.0 2.7
Input Reference Frequency = 19.44MHz; VCSO Frequency = 622.0800MHz
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
3
fax: 508-852-8456
www.micronetworks.com
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