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Part: M2006-03
Category:
Timing Circuits
-> SAW-Based clock modules
Description: CMTS Direct Conversion (Zero IF) Clock Source
Company: Integrated Circuit System
Datasheet: Download M2006-03 datasheet File size : 58 kB
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Datasheet text preview:
Integrated Circuit Systems, Inc.
Preliminary Information
M2006-03
DS_CLK_SEL
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
PIN ASSIGNMENT (9 x 9 mm SMT)
REF_CLK0 REF_CLK1 nUS_CLK REF_SEL US_CLK 20 VCCA GND VCC 19 18 17 16
GENERAL DESCRIPTION
The M2006-03 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for frequency translation and jitter attenuation of a master reference clock in a cable modem termination system (CMTS). External loop filter components allow tailoring of the PLL loop response. The M2006-03 includes a phaseslope limiting feature to prevent disruptive output clock phase changes upon input reference reselection.
27
26
24
23
25
VCC nREF_OUT REF_OUT M1_SEL M2_SEL VCC DNC DNC DNC
28 29 30 31 32 33 34 35 36 5 6 7 1 2 3 4 8 9
22
21
US_CLK_SEL1 US_CLK_SEL0 nDS_CLK_1 DS_CLK_1 GND nDS_CLK_0 DS_CLK_0 VCC GND
M2006-03
(Top View)
15 14 13 12 11 10
FEATURES
· · · · · · · · · · · · ·
Integrated SAW (surface acoustic wave) delay line VCSO center frequency of 491.52MHz
nOP_OUT
PLL phase slope limiter circuit Single-ended reference inputs support LVCMOS, LVTTL All output clocks are differential LVPECL compatible Two downstream clocks, frequency-selectable One upstream clocks, frequency-selectable REF_OUT always provides a 10.24MHz reference clock All output rising edges aligned to within 1nsec of selected input reference rising edge (unless M2_SEL = 1) Output duty cycle 47-53% worse case Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Selectable Frequencies (MHz) for M2006-03-491.5200
Input Ref. Clock: 2.048, 4.096, 10.24, or 20.48 MHz VCSO Frequency: 491.52 MHz Downstream Clock: 245.76 or 491.52 MHz Upstream Clock: 40.96, 81.92, 163.84, or 491.52 MHz Output Ref. Clock: 10.24 MHz
Table 1: Selectable Frequencies (MHz) for M2006-03-491.5200
SIMPLIFIED BLOCK DIAGRAM
M2006-03-491.52
VSCO
Reference Clock Input (20.48, 10.24, 4.096, or 2.048MHz) DS_CLK Pairs (491.52 or 245.76MHz) US_CLK Pair (491.52, 163.84, 81.92, 40.96MHz) REF_CLK Pair (10.24MHz)
MUX
DS Divider
1 0
Frequency Multiplying PLL
US Divider REF Divider
External Loop Filter M2_SEL
M1_SEL DS_CLK_SEL
US_CLK_SEL1:0
Figure 2: Simplified Block Diagram
M2006-03 Datasheet Rev 1.0
M2006-03 CMTS Direct Conversion (Zero IF) Clock Source
OP_OUT
nOP_IN
GND
GND
GND
OP_IN
nVC
Jitter 9ps rms, typical, over 100Hz to 12kHz Jitter 3ps rms, typical, over 12kHz to 1GHz
VC
Pa g e 1
Revision 011603
Integrated Circuit Systems, Inc.
Communications Modules
w w w. i c s t . c o m
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Integrated Circuit Systems, Inc.
M2006-03
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
Preliminary Information
DETAILED BLOCK DIAGRAM
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP OP_OUT RPOST nOP_OUT nVC VC
Ex ternal Loop Filter Components
M2006-03
MUX Phase Detector
OP_IN
nOP_IN
RIN
SAW Delay Line
REF_CLK1 REF_CLK0 REF_SEL
1 0
RIN Loop Filter Amplifier
Phase Locked Loop (PLL)
M1 Divider M1 = 24 or 48
Phase Shifter VCSO
DS CLOCK Divider
= 1 or 2
DS_CLK_0 nDS_CLK_0 DS_CLK_1 nDS_CLK_1 US_CLK nUS_CLK REF_OUT nREF_OUT
M2 Divider M2 = 1 or 5
US CLOCK Divider
= 1,3,6 or 12
REF Divider
= 2 or 1
M2_SEL
M1_SEL
DS_CLK_SEL
2 US_CLK_SEL1:0
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4, 9 5, 8 6, 7 11, 19, 27, 28, 33 12, 13 15, 16 20, 21 29, 30 Name GND OP_IN, nOP_IN nOP_OUT, OP_OUT nVC, VC VCC DS_CLK_0, nDS_CLK_0 DS_CLK_1, nDS_CLK_1 US_CLK_0, nUS_CLK nREF_OUT, REF_OUT, I/O Configuration Description
Ground Input Output Input Power Output No internal terminator
Power supply ground. Used for external loop filter. See Figure 4. Power supply connection, connect to +3.3V Downstream clock output pairs. Differential LVPECL. Upstream clock output pair. Differential LVPECL. Reference clock output pair. Differential LVPECL. Upstream Divider controls. LVCMOS/LVTTTL. For US_CLK_SEL1:0 : Logic 1 1 sets divider to 12 " 10 " ""6 " 01 " ""3 " 00 " ""1 Downstream Divider control. LVCMOS/LVTTTL: Logic 1 sets divider to 2 Logic 0 sets divider to 1 Reference clock input 1. LVCMOS/LVTTTL. Reference clock input 0. LVCMOS/LVTTTL. Reference clock input select. LVCMOS/LVTTTL: Logic 1 selects REF_CLK1 Logic 0 selects REF_CLK0 M1 Divider control. LVCMOS/LVTTTL: Logic 1 sets divider to 48 and REF Divider to 2 Logic 0 sets divider to 24 and REF Divider to 1 M2 Divider control. LVCMOS/LVTTTL: Logic 1 sets divider to 5 Logic 0 sets divider to 1 Do Not Connect.
Table 2: Pin Descriptions
17, 18
US_CLK_SEL0, US_CLK_SEL1
Input
Internal pull-down resistor1
22 23 24 25
DS_CLK_SEL REF_CLK1 REF_CLK0 REF_SEL
Input Input Input Input Input
Internal pull-down resistor1 Internal pull-down resistor1
31
M1_SEL
Internal pull-down resistor1
32 34, 35, 36
M2_SEL DNC
NOTE 1: For typical values of internal pull-down resistors, see DC Characteristics, Pull-down on pg. 5.
M2006-03 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
Pa g e 2 Communications Modules
Revision 011603
w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
M2006-03
CMTS DIRECT CONVERSION (ZERO IF) CLOCK SOURCE
Preliminary Information For the M2006-03-491.5200, which has a VCSO frequency of 491.52MHz, the four feedback divider values enable use with these corresponding input reference frequencies:
VSCO Frequency (MHz)
M2006-03-491.5200
FUNCTIONAL DESCRIPTION
The M2006-03 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). The VCSO center frequency is an integer multiple of the input reference frequency. The M2006-03 is available with a 491.52MHz VCSO frequency that is specifically designed to support DOCSIS modem applications. As such, the
M2006-03-491.520 (see "Ordering Information" on pg. 6) accepts input reference frequencies of: 2.048, 4.096, 10.24, and 20.48MHz.
÷
491.52
M Feedback = Divider Value 240 120 48 24
Input Reference Frequency (MHz) 2.048 4.096 10.24 20.48
M2006-03-491.5200
Table 4: Feedback Divider Values and Input Reference Frequencies
Because both inputs to the phase detector have the same frequency, the PLL can control the VCSO to keep it locked to the input reference clock. Post-PLL Dividers The M2006-03 also features three post-PLL dividers: the downstream ("DS") divider, the upstream ("US") divider, and the output reference ("REF") divider.
The DS Divider: Divides the VCSO frequency to produce one of two downstream output frequencies (1/2 or 1/1 of the VCSO frequency). The DS_CLK_SEL pin determines the DS Divider value.
DS_CLK_SEL
Input Reference The selectable reference inputs are applied to the REF_CLK1 and REF_CLK0 input pins as necessary. The REF_SEL pin selects the reference input:
· ·
REF_SEL = 1 selects REF_CLK1. REF_SEL = 0 selects REF_CLK0.
The selected reference clock is supplied directly to the phase detector of the PLL. The PLL The PLL (Phase Locked Loop) includes the phase detector, the VCSO, and two feedback dividers (labeled "M1 Divider" and "M2 Divider"). The product of the two feedback divider values equals the overall feedback divider value "M". M1 × M2 = M The M1_SEL and M2_SEL pins select the individual M1 and M2 divider values and, taken in combination, the overall feedback divider value ("M").
M2_SEL M1_SEL
1 0
DS Value Downstream Output Frequencies (MHz) 2 245.76 1 491.52
M2006-03-491.5200
Table 5: Downstream Divider Selector, Values, and Frequencies
The US Divider: Divides the VCSO frequency to produce
one of four upstream output frequencies (1/12, 1/6, 1/3 or 1/1 of the VCSO frequency). The US_CLK_SEL1 and US_CLK_SEL0 pins determine the US Divider value.
US_CLK_SEL1 US_CLK_SEL0 US Value
M2 M1 Overall Feedback × Value Value = Divider "M" Value 5 1 48 24 48 24 240 120 48 24
1 1 0 0
1 0 1 0
12 6 3 1
Upstream Output Frequencies (MHz) 40.96 81.92 163.84 491.52
M2006-03-491.5200
Table 6: Upstream Divider Selectors, Values, and Frequencies
1 1 0 0
1 0 1 0
The REF Divider: Used along with the M1 divider value to ensure that the output system reference clock always equals the VCSO frequency divided by 48. The M1_SEL pin determines the REF Divider value.
M2006-03-491.5200
Table 3: Combined Feedback Divider Selectors and Values
"M" is used to divide the VCSO frequency so that it matches the input reference frequency. The relationship between the VCSO frequency, the M Divider, and the input reference frequency is: Fvcso ÷ M = Fref_in M2006-03 Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
REF M1_SEL Value 1 0 1 2
REF Output VCSO M1 REF × Frequency ÷ = Frequency Value Value (MHz) (MHz) 48 1 491.52 10.24 24 2
M2006-03-491.5200
Table 7: M1 Selector and REF Divider Values and Frequencies
Pa g e 3 Communications Modules
Revision 011603
w w w. i c s t . c o m
tel (508) 852-5400
Others parts begin by m2
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