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Part: M2005-02-622.0800
Category:
Timing Circuits
-> Frequency Translation
Description: Frequencytranslation PLL
Company: Integrated Circuit System
Datasheet: Download M2005-02-622.0800 datasheet File size : 58 kB
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Datasheet text preview:
Micro Networks
An Integrated Circuit Systems Company
M2005-02
Preliminary Specifications
M2005-02
Frequency Translator
DESCRIPTION
The M2005-02 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Synthesizer in a 9mm x 9mm surface mount package. The internal high "Q" SAW filter provides low jitter signal performance and determines the maximum output frequency of the VCSO. A programmable output divider can divide the VCSO frequency by a factor of 4 to achieve an output as low as 77.76MHz with a 311.04MHz VCSO.
FEATURES
Output Clock Frequency up to 700MHz Differential LVPECL Outputs Internal Low-jitter SAW-based Oscillator Intrinsic Jitter <1ps rms (12kHz - 20MHz) Jitter Attenuation of Input Reference Clock Dual Input MUX Configurable Loop and Output Dividers Tunable Loop Filter Response Single 3.3V Supply Small 9mm x 9mm SMT Package HOLD Mode During Loss of Input Reference Clock
APPLICATIONS
The input to the Frequency Synthesizer is provided by selecting between one of two input reference clocks. The maximum input frequency is 250 MHz. Serial control of the input divider, the feedback divider, and output divider is provided via the configuration logic. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. A HOLD feature freezes the VCSO frequency so that a stable output clock can be maintained when both input reference clocks are lost. The bandwidth control, low phase noise, and HOLD features make the M2005-02 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in OC-3 through OC-192 applications.
ABSOLUTE MAX RATINGS Inputs, VI : ....... -0.5 to VCC+0.5V Output, VO : ....... -0.5 to VCC+0.5V Supply Voltage, VCC : ......... 4.6 V Storage Temperature, TSTO : .... -45°C to +100°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
SONET / SDH / 10GbE System Synchronization Add / Drop Muxes, Access and Edge Switches Line Card System Clock Cleaner / Translator Optical Module Clock Cleaner / Translator
ISO 9001 Registered
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
1
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL BLOCK DIAGRAM
M2005-02
Preliminary Specifications
The internal PLL will adjust the VCSO output frequency to be M (feedback divider) divided by P (input divider) times the selected input reference clock frequency. Note that the ratio of M/P times input frequency must be such that it falls within the "lock" range of the VCSO. The M divider (17-bits) can be programmed for a maximum value of 131,071 and a minimum value of 4. The P divider (9-bits) can be set to a maximum value of 511 and a minimum value of 1. The N output divider can be programmed to divide the VCSO output frequency by 1, or 4 and provide a 50% output duty cycle. The M2005-02 is serially programmed via a 3 wire interface. Figure 1 shows the timing diagram for serial programming. The relationship between the VCSO frequency, the M & P dividers, and the input REF_CLK is defined as follows: F VCSO = F REF_CLK x M P When the N output divider is included, the
complete relationship for the output frequency is defined as: M FOUT = F VCSO = F REF_CLK x N NxP The N1 input can be hard wired to set the N divider to a specific state that will automatically occur during power-up. Serial operation occurs when S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divider and N output divide values are latched on the HIGH-to- LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. When the HOLD input is asserted the M2005-02 will revert back to the initial accuracy of the VCSO and remain at that frequency until the HOLD signal is returned LOW.
RLOOP
CLOOP
RPOST CPOST CPOST
Ex ternal Loop Filter Components
RLOOP
CLOOP
RPOST nOP_OUT nVC VC 0 Frequency Hold 1 Phase Shifter VCSO SAW Delay Line
M2005-02
MUX
OP_IN Phase Detector RIN
nOP_IN OP_OUT
REF_CLK1 REF_CLK0 REF_SEL
1 0
R Divider R=1,2,4 to 511 RIN Loop Filter Amplifier M Divider M = 3 to 131,071
S_DATA S_CLK S_LOAD nP_LOAD
P Divider P = 1 or 4 Serial / Parallel Configuration Register
FOUT nFOUT
6 M5:0
P1
HOLD
MR
FIGURE 1
S_DATA Low Low Null N1 N0 Null Null Null M5 M4 M3 M2 M1 M0
S_CLK
S_LOAD
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
2
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL DESCRIPTION LOOP FILTER FIGURE 2
Rloop OP_IN Cloop
M2005-02
Preliminary Specifications
The M2005-02 requires the use of an external loop filter via the provided filter pins. Due to the differential design, the implementation requires two identical RC filters as shown in Figure 2.
Rpost nVc Cpost
nOP_OUT OP_OUT Cpost nOP_IN Rloop Cloop Rpost Vc
TABLE 1. RECOMMENDED LOOP FILTER VALUES REF_CLK Frequency 19.44MHz VCSO Frequency 622.0800MHz M N Fout Rloop Cloop Rpost Cpost
32
1
622.0800MHz
5K
1MF
50K
100pf
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
3
fax: 508-852-8456
www.micronetworks.com
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