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Part: M2004-02
Category:
Timing Circuits
-> Frequency Translation
Description: Frequencytranslation PLL
Company: Integrated Circuit System
Datasheet: Download M2004-02 datasheet File size : 58 kB
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Datasheet text preview:
Micro Networks
An Integrated Circuit Systems Company
M2004-02
Preliminary Specifications
M2004-02
Frequency Synthesizer
DESCRIPTION
The M2004-02 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Synthesizer in a 9mm x 9mm surface mount package. The internal high "Q" SAW filter provides low jitter signal performance and determines the maximum output frequency of the VCSO. A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz. The input to the Frequency Synthesizer is provided by selecting between a differential input clock or a single ended input clock. The output frequency is an integer multiple of the input reference frequency. The multiplying factor is programmed via a 6 bit parallel address. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. The bandwidth control, low phase noise, and HOLD features make the M2004-02 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in OC-3 through OC-192 applications.
FEATURES
Output Clock Frequency up to 700MHz Internal Low-jitter SAW-based Oscillator Intrinsic Jitter <1ps rms (12kHz - 20MHz) Differential Input Compatible with LVPECL, LVDS, HSTL, SSTL, etc. Dual Input MUX Parallel Programming Tunable Loop Filter Response Differential LVPECL Outputs 3.3V Operation Small 9mm x 9mm SMT Package
APPLICATIONS
SONET / SDH / 10GbE System Synchronization Add / Drop Muxes, Access and Edge Switches Line Card System Clock Cleaner / Translator Optical Module Clock Cleaner / Translator
ISO 9001 Registered
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
1
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL BLOCK DIAGRAM
M2004-02
Preliminary Specifications
Functional Description:
The internal PLL will adjust the VCSO output frequency to be M (feedback divider) times the selected input reference clock frequency. Note that the product of M x the input reference frequency
The multiplying factor is programmed via a 6-bit parallel bus. The relationship between the VCSO frequency, the M divider, and the Differential Input reference clock is defined as follows: F VCSO = F REF_CLK x M
OP_IN
nOP_IN
OP_OUT
nOP_OUT
Vc
nVc
When the N output divider is included, the complete relationship for the output frequency is defined as:
F OUT nF OUT
DIF_REF 0 nDIF_REF 0
Mux
REF_CLK
Phase Detector & Active Loop Filter
VCSO
Output Divider
FOUT = F VCSO = F REF_CLK x M N N The N1 input can be hard wired to set the N divider to a specific state that will automatically occur during power-up.
REF_SEL
+M
N1
M5:M0
Parallel Programming Interface
MR
must be such that it falls within the "lock" range of the VCSO. The N output divider can be programmed to divide the VCSO output frequency by 1, 2, 4, or 8 and provide a 50% output duty cycle.
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
2
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company FUNCTIONAL DESCRIPTION LOOP FILTER FIGURE 2
Rloop OP_IN Cloop
M2004-02
Preliminary Specifications
The M2004-02 requires the use of an external loop filter via the provided filter pins. Due to the differential design, the implementation requires two identical RC filters as shown in Figure 2.
Rpost nVc Cpost
nOP_OUT OP_OUT Cpost nOP_IN Rloop Cloop Rpost Vc
TABLE 1. RECOMMENDED LOOP FILTER VALUES REF_CLK Frequency 19.44MHz VCSO Frequency 622.0800MHz M N FOUT Rloop Cloop Rpost Cpost
32
1
622.0800MHz
5k
1MF
20k
250pf
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
3
fax: 508-852-8456
www.micronetworks.com
Others parts begin by m2
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