Digchip : Database on electronics components
 
Member, Distributor  
Log In
Email:
Password:


Part: IS41C16257-60T

Category:
 Memory
   -> DRAM
     -> EDO/FPM DRAM

Description:

Company: Integrated Circuit Solution

Datasheet: Download IS41C16257-60T datasheet     File size : 152 kB

Request For quote: Find where to buy IS41C16257-60T



Datasheet text preview:
IIS41C162576257 S41C1 S41 V 2 7 IIS4L116V516257 L
256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
FEATURES
Fast access and cycle time TTL compatible inputs and outputs Refresh Interval: 512 cycles/8 ms Refresh Mode: 4)5-Only, +)5-before-4)5 (CBR), Hidden JEDEC standard pinout Single power supply: 5V ± 10% (IS41C16257) 3.3V ± 10% (IS41LV16257) Byte Write and Byte Read operation via two +)5 Available in 40-pin SOJ and TSOP-2
DESCRIPTION
The 1+51 IS41C16257 and the IS41LV16257 are 262,144 x 16-bit high-performance CMOS Dynamic Random Access Memory. Fast Page Mode allows 512 random accesses within a single row with access cycle time as short as 12 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes these devices ideal for use in 16-, 32-bit wide data bus systems. These features make the IS41C16257 and the IS41LV16257 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications.
KEY TIMING PARAMETERS
Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) -35 35 10 18 12 60 -50 50 14 25 20 90 -60 60 15 30 25 110 Unit ns ns ns ns ns
PIN CONFIGURATIONS 40-Pin TSOP-2
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8
Min. Read/Write Cycle Time (tRC)
40-Pin SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A8 I/O0-I/O15 WE OE RAS UCAS LCAS Vcc GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Power Ground No Connection
NC NC WE RAS NC A0 A1 A2 A3 VCC
11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 25 24 23 22 21
NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
NC WE RAS NC A0 A1 A2 A3 VCC
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR002-0C
1
" DRAM
The IS41C16257 and the IS41LV16257 are packaged in a 40-pin, 400mil SOJ and TSOP-2.
IS41C16257 IS41LV16257
FUNCTIONAL BLOCK DIAGRAM
OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC
CAS
WE
OE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O15
" DRAM
ROW DECODER
MEMORY ARRAY 262,144 x 16
ADDRESS BUFFERS A0-A8
2
Integrated Circuit Solution Inc.
DR002-0C
IS41C16257 IS41LV16257
TRUTH TABLE
Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write(1,2) Hidden Refresh2) RAS-Only Refresh CBR Refresh(3) RAS H L L L L L L L Read LHL Write LHL L HL LCAS UCAS H H L L L H H L L H L L L H L L L H L L L L H L WE X H H H L L L HL H L X X OE X L L L X X X LH L X X X Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT DIN Lower Byte, DIN Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DIN DOUT, DIN DOUT DOUT High-Z High-Z
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Circuit Solution Inc.
DR002-0C
3
" DRAM


Others parts begin by is
IS-1   IS-2   IS-3   IS-4   IS-5   IS-6   IS-7   IS-8   IS-9   IS-10   IS-11   IS-12   IS-13   IS-14   IS-15   IS-16   IS-17   IS-18   IS-19   IS-20   IS-21   IS-22   IS-23   IS-24   IS-25   IS-26   IS-27   IS-28   IS-29   IS-30   IS-31   IS-32   IS-33   IS-34   IS-35   IS-36   IS-37   IS-38   IS-39   IS-40   IS-41   IS-42   IS-43   IS-44   IS-45   IS-46   IS-47   IS-48   IS-49   IS-50   IS-51   IS-52   IS-53   IS-54   IS-55   IS-56   IS-57   IS-58   IS-59   IS-60   IS-61   IS-62