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Part: HYMD512M646ALFS8-K
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> SO DIMM
-> 1 GB
Description:
Company: Hynix Semiconductor
Datasheet: Download HYMD512M646ALFS8-K datasheet File size : 904 kB
Request For quote: Find where to buy HYMD512M646ALFS8-K
Datasheet text preview:
128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646A(L)FS8-J/M/K/H/L
DESCRIPTION
Preliminary
Hynix HYMD512M646A(L)FS8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMD512M646A(L)FS8-J/M/K/H/L series consists of eight 128Mx8 DDR MCP SDRAM in FBGA packages on a 200pin glass-epoxy substrate. Hynix HYMD512M646A(L)FS8-J/M/K/H/L series provide a high performance 8-byte interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD512M646A(L)FS8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD512M646A(L)FS8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
· · · · · · 1GB (128M x 64) Unbuffered DDR SO-DIMM based on 128Mx8 DDR MCP SDRAM 200-pin small outline dual in-line memory module (SO-DIMM) 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz/166MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock · · · · · · · · Data inputs on DQS centers when write (centered DQ) Data strobes synchronized with output data for read and input data for write Programmable CAS Latency 2 / 2.5 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 8192 refresh cycles / 64ms
·
ORDERING INFORMATION
Part No.
HYMD512M646A(L)FS8-J HYMD512M646A(L)FS8-M HYMD512M646A(L)FS8-K HYMD512M646A(L)FS8-H HYMD512M646A(L)FS8-L V D D =2.5V V D D Q =2.5V
Power Supply
Clock Frequency
166MHz (*DDR333) 133MHz (*DDR266:2-2-2) 133MHz (*DDR266A) 133MHz (*DDR266B) 100MHz (*DDR200)
Interface
Form Factor
SSTL_2
200pin Unbuffered SO-DIMM 67.6mm x 31.75mm x 1mm
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / June 2003 1
HYMD512M646A(L)FS8-J/M/K/H/L
PIN DESCRIPTION
Pin CK0, /CK0, CK1, /CK1 CS0, CS1 CKE0, CKE1 /RAS, /CAS, /WE A0 ~ A13 BA0, BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7 VDD Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Pin V DDQ VSS VREF VDDSPD SA0~SA2 S CL S DA VDDID DU NC Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O VDD Identification Flag Do not Use No Connection
PIN ASSIGNMENT
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Name VREF VSS DQ0 DQ1 V DD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Nam e VREF VSS DQ 4 DQ 5 VDD DM 0 DQ 6 VSS DQ 7 DQ12 V DD DQ13 DM1 VSS DQ14 DQ15 V DD V DD VSS VSS DQ20 DQ21 V DD DM2 DQ22 Pin 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 Name VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 V DD NC NC VSS NC NC VDD NC DU VSS NC NC VDD CKE1 NC A12 Pin 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 Name VSS DQ23 DQ28 VDD DQ 2 9 DM 3 VSS DQ30 DQ31 VDD NC NC VSS NC NC V DD NC DU VSS VSS VDD V DD CKE0 DU A11 Pin 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Nam e A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 A13 VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS Pin 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Nam e A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS Pin 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 199 Name DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDID Pin 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 200 Nam e DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM 6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM 7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
197 VDDSPD 198
Rev. 0.2 / June 2003
2
HYMD512M646A(L)FS8-J/M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
C KE 1 CKE0 /CS1 /CS0 DQS0 DM 0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1 DQ32 DQ33 DQ34
DQS4 DM 4
DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1
D0
DQ35 DQ36 DQ37 DQ38 DQ39
D4
DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1
DQS5 DM 5
DQ40 DQ41 DQ42 DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1
D1
DQ43 DQ44 DQ45 DQ46 DQ47
D5
DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM DQS /CS0 /CS1 /CKE0 /CKE1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
DQS6 DM 6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1
D2
D6
DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1
DQS7 DM 7
DQ56 DQ57 DQ58 DM I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1
D3
DQ59 DQ60 DQ61 DQ62 DQ63
D7
VDD SPD
VDD /VDDQ
SPD DO-D15 DO-D15 DO-D15
Strap:see Note 4
Serial PD SCL WP A0 A1 A2 SA2 SDA
VREF VSS VDDID
SA0 SA1
BA0-BA1 A0-A13 /RAS /CAS /W E
BA0-BA1 : SDRAMs D0-D7 A0-A13 : SDRAMs D0-D7 /RAS : SDRAMs D0-D7 /CAS : SDRAMs D0-D7 /WE : SDRAMs D0-D7
Note : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors : 22 Ohms ? 5%. 4. VDDID strap connections (for memory device VDD, VDDQ) : STRAP OUT (OPEN) : VDD = VDDQ STRAP IN (VSS) : VDD ? VDDQ
Rev. 0.2 / June 2003
3
Others parts begin by hy
HY-1 HY-2 HY-3 HY-4 HY-5 HY-6 HY-7 HY-8 HY-9 HY-10 HY-11 HY-12 HY-13 HY-14 HY-15 HY-16 HY-17 HY-18 HY-19 HY-20 HY-21 HY-22 HY-23 HY-24 HY-25 HY-26 HY-27 HY-28 HY-29 HY-30 HY-31 HY-32 HY-33 HY-34
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