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Part: HYMD216646AL6-H
Category:
Memory
-> DRAM
-> DDR SDRAM
-> Modules
-> Unbuffered DIMM
-> 128 MB
Description:
Company: Hynix Semiconductor
Datasheet: Download HYMD216646AL6-H datasheet File size : 904 kB
Request For quote: Find where to buy HYMD216646AL6-H
Datasheet text preview:
16Mx64 bits
Unbuffered DDR SDRAM DIMM
HYMD216646A(L)6-M/K/H/L
DESCRIPTION
Hynix HYMD216646A(L)6-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Lin Memory Modules (DIMMs) which are organized as 16Mx64 high-speed memory arrays. Hynix HYMD216646A(L)6-M/K/ H/L series consists of four 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HMD216646A(L)6-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD216646A(L)6-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched hed on the rising edges of the clock, Data, Data strobes(UDQS/LDQS) and Write data masks(UDM/ LDM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD216646A(L)6-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
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128MB (16M x 64) Unbuffered DDR DIMM based on 16Mx16 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock
· · · · · · · ·
Data inputs on DQS centers when write (centered DQ) Data strobes synchronized with output data for read and input data for write Programmable CAS Latency 2 / 2.5 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode tRAS Lock-out function supported Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 8192 refresh cycles / 64ms
·
ORDERING INFORMATION
Part No.
HYMD216646A(L)6-M HYMD216 646A(L) 6-K HYMD216 646A(L) 6-H HYMD216 646A(L) 6 -L V D D =2.5 V V D D Q =2.5V
Power Supply
Clock Frequency
133MHz (*DDR266:2-2-2) 133MHz (*DDR266A) 133MHz (*DDR266B) 100MHz (*DDR200)
Interface
Form Factor
SSTL_2
184pin Unbuffered DIMM 5.25 x 1.25 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2/May. 02 1
HYMD216646A(L)6-M/K/H/L
PIN DESCRIPTION
Pin CK1,/CK1,CK2,/CK2 /CS0 CKE0 /RAS, /CAS, /WE A0 ~ A12 BA0, BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7 VDD Pin Description Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply Pin VDDQ VSS V REF VDDSPD SA0~SA2 SCL S DA VDDID DU NC Pin Description DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2PROM Address Inputs E2PROM Clock E2PROM Data I/O VDD Identification Flag Do not Use No Connection
PIN ASSIGNMENT
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name V REF DQ 0 VSS DQ 1 DQS0 DQ 2 VDD DQ 3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 53 54 55 56 57 58 59 60 61 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Name A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ 2 7 A2 V ss A1 CB 0 * CB1* VDD DQS8* A0 CB 2 * VSS CB3* BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Nam e VDDQ /WE DQ41 /CAS VSS DQ S 5 DQ42 DQ43 V DD NC DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Name VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC A13* VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 V DDQ BA2* DQ20 A12 VSS DQ 2 1 A11 DM 2 VDD DQ22 A8 DQ23 145 146 147 148 149 150 151 152 153 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 key VSS DQ36 DQ37 VDD DM 4 DQ38 DQ39 VSS DQ44 Nam e VSS A6 DQ28 DQ29 VDDQ DM 3 A3 DQ30 VSS DQ31 CB4* CB5* VDDQ CK0* /CK0* VSS DM 8 * A10 CB6* V DDQ CB7* Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Name /RAS DQ45 VDDQ /CS0 /CS1 DM 5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.2/May. 02
2
HYMD216646A(L)6-M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
/CS0
/CS
DQS1 DM1
/CS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS0 DM0
LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9
D0
DQS5 DM5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS4 DM4
LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9
D2
/CS
DQS3 DM3
/CS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS2 DM2
LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9
D1
DQS7 DM7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS6 DM6
LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9
D3
Serial PD *Clock Wiring WP A0 SA0 A1 SA1 A2 SA2 *CK0,/CK0 *CK1,/CK1 *CK2,/CK2 NC 2 SDRAMs 2 SDRAMs SDA Clock Input SDRAMs VDDSPD VDD/VDDQ VREF VSS VDDID
.
* Wire per clock loading table/wiring diagrams
. == . . ...= ..
SPD D0 - D3 D0 - D3 D0 - D3
Strap:see Note 4
BA0-BA1 A0 A12 /RAS /CAS CKE0 /W E
BA0-BA1 : SDRAMs D0 - D3 A0 - A12 : SDRAMs D0 - D3 /RAS : SDRAMs D0 - D3 /CAS : SDRAMs D0 - D3 CKE : SDRAMs D0 - D3 /WE : SDRAMs D0 - D3
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown 3. DQ, DQS, DM/DQS resistors : 22Ohms+/-5% 4. VDDID strap connections (for memory device VDD, VDDQ) : Strap out :(open) : VDD=VDDQ Strap In (Vss) : VDD= VDDQ
Rev. 0.2/May. 02
3
Others parts begin by hy
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