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Part: HYM7V65401BLTQG-10S
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> 64 MB
-> ->SO DIMM
Description:
Company: Hynix Semiconductor
Datasheet: Download HYM7V65401BLTQG-10S datasheet File size : 904 kB
Request For quote: Find where to buy HYM7V65401BLTQG-10S
Datasheet text preview:
4Mx64 bits PC100 SDRAM SO DIMM
based on 4Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM7V65401B Q-Series DESCRIPTION
The Hynix HYM7V65401B Q-Series are 4Mx64bits Synchronous DRAM Modules. The modules are composed of four 4Mx16bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB. The HYM7V65401B Q-Series are Small Outline Dual In-line Memory Modules suitable for easy interchange and addition of 32Mbytes memory. The HYM7V65401B Q-Series are offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
· PC100MHz support · 144pin SDRAM SO DIMM · Serial Presence Detect with EEPROM · 1.00" (25.40mm) Height PCB with Double Sided components · Single 3.3 ± 0.3V power supply · All devices pins are compatible with LVTTL interface · Data mask function by DQM · SDRAM internal banks : four banks · Module bank : one physical bank · Auto refresh and self refresh · 4096 refresh cycles / 64ms · Programmable Burst Length and Burst Type -. 1, 2, 4, 8, or Full Page for Sequential Burst -. 1, 2, 4 or 8 for Interleave Burst · Programmable /CAS Latency -. 2, 3 Clocks
ORDERING INFORMATION
PART NO. HYM7V65401BTQG-8 HYM7V65401BTQG-10P HYM7V65401BTQG-10S HYM7V65401BLTQG-8 HYM7V65401BLTQG-10P HYM7V65401BLTQG-10S MAX. FREQUENCY 125MHz 100MHz 100MHz 125MHz 100MHz 100MHz 4 Banks 4K Low Power Normal TSOP-II Gold INTERNAL BANK REF. POWER SDRAM PACKAGE PLATING
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 1 Rev. 1.2/Dec. 01
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series PIN DESCRIPTION
PIN NAME CK0, CK1 CKE0 /S0 BA0, BA1 Clock Inputs Clock Enable Chip Select SDRAM Bank Address DESCRIPTION The System Clock Input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Enables or disables all inputs except CK, CKE and DQM. Select bank to be activated during /RAS activity. Select bank to be read/written during /CAS activity Row address : RA0~RA11, Column address : CA0~CA7 Auto-precharge flag : A10 /RAS define the operation. Refer to the function truth table for details. /CAS define the operation. Refer to the function truth table for details. /WE define the operation. Refer to the function truth table for details. Controls output buffers in read mode and masks input data in write mode. Multiplexed data input/output pins Power supply for internal circuits and input/output buffers Ground Serial Presence Detect Clock Input Serial Presence Detect Data input/output No Connect or Don't Use
A0~A11
Address Inputs
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE DQM0~DQM7 DQ0~DQ63 VCC VSS SCL SDA NC
Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output No Connect
Rev. 1.2/Dec. 01
2
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series PIN ASSIGNMENTS
FRONT SIDE PIN NO. NAME 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC PIN NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 BACK SIDE NAME VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 DQ45 DQ46 DQ47 VSS NC NC FRONT SIDE PIN NO. NAME 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 NC NC VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10/AP VCC DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC PIN NO. 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 BACK SIDE NAME NC *CK1 VSS NC NC VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 VCC DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
Voltage Key
61 63 65 67 69 CK0 VCC /RAS /WE /S0 62 64 66 68 70 CKE0 VCC /CAS NC NC
Note : *. CK1 is connected with termination R/C. (Refer to the Block Diagram.)
Rev. 1.2/Dec. 01
3
Others parts begin by hy
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