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Part: HYM72V64C756K8M
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Modules
-> 256 MB
Description: 64Mx72 Bits PC100 Sdram Registered Dimm With Pll, Based on 32Mx8 Sdram With Lvttl, 4 Banks & 8K Refresh
Company: Hynix Semiconductor
Datasheet: Download HYM72V64C756K8M datasheet File size : 904 kB
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Datasheet text preview:
64Mx72 bits PC100 SDRAM Registered DIMM
with PLL, based on 32Mx8 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V64C756K8M Series
DESCRIPTION
The HYM72V64C756K8M H-Series are high speed 3.3-Volt synchronous dynamic RAM Modules composed of eighteen 32Mx8 bit Synchronous DRAMs in 54-pin TSOPII, two 48-pin TSSOP Register Buffers, one 24-pin TSSOP PLL and 8-pin TSSOP 2K bit EEPROM on a 168-pin glass-epoxy printed circuit board. One 0.22µF and one 0.0022µF decoupling capacitors per each SDRAM are mounted on the module. The HYM72V64C756K8M H-Series are gold plated socket type Dual In-line Memory Modules suitable for easy interchange and addition of 512M bytes memory. All addresses, data and control inputs are latched on the rising edge of the master clock input. The data paths are internally pipelined to achieve very high bandwidths.
FEATURES
· · · · · · · · · · · 1.125" (28.56mm) PCB Height 168-Pin Registered DIMM with Double Sided ECC support One 0.22µF and one 0.0022µF decoupling capacitors adopted Serial Presence Detect with Serial EEPROM Two Register Buffers & one Inverter used (with PLL) Supports Flow-through or Register mode by Pin No. 147 (REGE) Meets all the other JEDEC specifications Single 3.3V±0.3V power supply All device pins are LVTTL compatible 8192 refresh cycles every 64ms · Auto precharge/precharge all banks by A10 flag · Possible to assert random column address every clock cycle · Interleaved auto refresh mode · Programmable burst lengths and sequences - 1,2,4,8,full page for Sequential type - 1,2,4,8 for Interleave type · Programmable /CAS latency ; 2,3 clocks · Support clock suspend/power down mode by CKE0Hynix · Data mask function by DQM · Mode register set programming · Burst termination command · Self refresh provides minimum power, full internal
ORDERING INFORMATION
Part No.
HYM72V64C756K8M-8 HYM72V64C756K8M-S
Clock Frequency
125MHz
Internal Bank
4 Banks
Ref.
Power
SDRAM Package
TSOP-II
Plating
8K
Normal
Gold
100MHz
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Apr. 2001
PC100 SDRAM Registered DIMM
HYM72V64C756K8M Series
PIN DESCRIPTION
PIN CK0~CK3 CKE0, CKE1 /S0 ~ /S3 BA0, BA1 A0 ~ A12 /RAS, /CAS, /WE REGE DQM0~DQM7 DQ0 ~ DQ63 CB0 ~ CB7 VCC VSS SCL SDA SA0~2 WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Register Enable Data Input/Output Mask Data Input/Output Check Bit Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Register Enable pin which permits the DIMM to operateion in Buffered Mode when REGE input is Low, in Registered Mode when REGE input is High Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Check bits for ECC Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM No connection
Rev. 0.1/Apr.2001
2
PC100 SDRAM Registered DIMM
HYM72V64C756K8M Series
PIN ASSIGNMENTS
FRONT SIDE PIN NO.
1 2 3 4 5 6 7 8 9 10
BACK SIDE PIN NO.
85 86 87 88 89 90 91 92 93 94
FRONT SIDE PIN NO.
41 42 43 44 45 46 47 48 49 50 51 52
BACK SIDE PIN NO.
125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
NAME
VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7
NAME
VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39
NAME
VCC CK0 VSS NC /S2 DQM2 DQM3 NC VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VCC DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VCC
NAME
*CK1 A12 VSS CKE0 /S3 DQM6 DQM7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VCC DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC SA0 SA1 SA2 VCC
Architecture Key
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC /WE DQM0 DQM1 /S0 NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC /CAS DQM4 DQM5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Voltage Key
Note : * CK1 ~ CK3 are connected with termination R/C (Rsfer to the block diagram)
Rev. 0.1/Apr.2001
3
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