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Part: HY62SF16806A-DMI

Category:
 Memory
   -> SRAM
     -> Low Power
       -> 8 Mb
             -> Super Low Power Slow SRAM

Description:

Company: Hynix Semiconductor

Datasheet: Download HY62SF16806A-DMI datasheet     File size : 504 kB

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Datasheet text preview:
HY62SF16806A Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM
Revision History
Revision No 00 01 History Initial Draft Change Logo - Hyundai à Hynix AC Parameter is changed - tCHZ : 30ns --> 20ns - tBHZ : 30ns --> 20ns - tOHZ : 30ns --> 20ns Change DC Parameter - Icc1(1us) : 5mA à 4mA Change Data Retention - IccDR(LL) : 25uA à 15uA Change AC Parameter - tOE : 40ns à 35ns@70ns Draft Date Apr.10.2001 Apr.28.2001 Remark Preliminary
02
Jul.18.2001
03
Jan.28.2002
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.03 /Jan. 2002 Hynix Semiconductor
HY62SF16806A
FEATURES
· Fully static operation and Tri-state output · TTL compatible inputs and outputs The HY62SF16806A is a high speed, super low · Battery backup(LL/SL-part) power and 8Mbit full CMOS SRAM organized as - 1.2V(min) data retention 524,288 words by 16bits. The HY62SF16806A · Standard pin configuration uses high performance full CMOS process - 48-uBGA technology and is designed for high speed and low power circuit technology. It is particularly wellsuited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. Product Voltage Speed Operation Standby Current(uA) Temperature No. (V) (ns) Current/Icc(mA) LL SL (°C) HY62SF16806A-C 1.7~2.3 70/85/100 3 25 8 0~70 HY62SF16806A-I 1.7~2.3 70/85/100 3 25 8 -40~85 Note 1. C : Commercial, I : Industrial 2. Current value is max.
DESCRIPTION
PIN CONNECTION ( Top View )
1 2 /OE /UB 3 A0 A3 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 /CS1 IO2 IO4 IO5 IO6 6 CS2
BLOCK DIAGRAM
ROW DECODER SENSE AMP
A B C D E F G H
/LB IO9
I/O1
COLUMN DECODER
IO1
ADD INPUT BUFFER PRE DECODER
I/O8 DATA I/O BUFFER
IO10 IO11 A5 Vss Vcc IO12 A17 IO13 Vss
IO3 Vcc Vss IO7
A18
MEMORY ARRAY 512K x 16
WRITE DRIVER
I/O9
BLOCK DECODER
IO15 IO14 A14 IO16 NC A18 A8 A12 A9
I/O16
/WE IO8 A11 NC
/CS1 CS2 /OE /LB /UB /WE
PIN DESCRIPTION
Pin Name /CS1, CS2 /WE /OE /LB /UB Pin Function Chip Select Write Enable Output Enable Lower Byte Control(I/O1~I/O8) Upper Byte Control(I/O9~I/O16) Pin Name I/O1~I/O16 A0~A18 Vcc Vss NC Pin Function Data Inputs / Outputs Address Inputs Power(1.7V~2.3V) Ground No Connection
Rev.03 /Jan. 2002
2
HY62SF16806A
ORDERING INFORMATION
Part No. Speed HY62SF16806A-DMC 70/85/100 HY62SF16806A-SMC 70/85/100 HY62SF16806A-DMI 70/85/100 HY62SF16806A-SMI 70/85/100 Note 1. C : Commercial, I : Industrial Power LL-part SL-part LL-part SL-part Package uBGA uBGA uBGA uBGA Temp. C C I I
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VIN, VOUT Vcc TA Parameter Input/Output Voltage Power Supply Operating Temperature Rating -0.2 to 3.6 -0.2 to 4.6 0 to 70 -40 to 85 -55 to 150 1.0 260 · 10 Unit V V °C °C °C W °C · sec Remark
HY62SF16806A-C HY62SF16806A-I
TSTG Storage Temperature PD Power Dissipation TSOLDER Ball Soldering Temperature & Time Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1 H X X L L L CS2 X L X H H H /WE X X X H H H /OE X X X H H L /LB X X H L X L H L L H L /UB X X H X L H L L H L L
Mode
Deselected Output Disabled Read
L
H
L
X
Write
I/O Pin I/O1~I/O8 I/O9~I/O16 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z DOUT DOUT DOUT DIN Hi-Z Hi-Z DIN DIN DIN
Power Standby Active Active
Active
Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. UB, LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8. When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.03 /Jan. 2002
2


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