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Part: HY5V62CF
Category:
Memory
-> DRAM
-> SDR SDRAM
-> 64 Mb
Description: 4 Banks X 512K X 32Bit Synchronous DRAM
Company: Hynix Semiconductor
Datasheet: Download HY5V62CF datasheet File size : 908 kB
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Datasheet text preview:
HY5V62CF
4 Banks x 512K x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY5V62C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V62C is organized as 4banks of 524,288x32. HY5V62C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
· · · · JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 · · Internal four banks operation · Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks · · · Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst ·
ORDERING INFORMATION
Part No.
HY5V62CF-7 HY5V62CF-S
Clock Frequency
143MH z
Power
Normal
Organization
4Banks x 512Kbits x32
Interface
LVTTL
Package
90Ball FBGA
100MH z
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/Nov. 01
HY5V62CF
PIN CONFIGURATION
1 A
DQ 26 DQ24 VSS VDD DQ 23 DQ 21
2
3
4
5
6
7
8
9
B
DQ 28 VDDQ VSSQ VDDQ VSSQ DQ 19
C
VSSQ DQ27 DQ 25 DQ 22 DQ 20 VDDQ
D
VSSQ DQ29 DQ 30 DQ 17 DQ 18 VDDQ
E
VDDQ DQ31 NC NC DQ 16 VSSQ
F
VSS DQM3 A3 A2 DQM2 VDD
G
A4 A5 A6 A10 A0 A1
H
A7 A8 NC
T o p View
(1 1 m m x1 3 m m )
NC BA1 NC
J
CLK CKE A9 BA0 CS# RAS#
K
DQM1 NC NC CAS# W E# DQM0
L
VDDQ DQ8 VSS VDD DQ7 VSSQ
M
VSSQ DQ 10 DQ9 DQ6 DQ5 VDDQ
N
VSSQ DQ 12 DQ 14 DQ1 DQ3 VDDQ
P
DQ 11 VDDQ VSSQ VDDQ VSSQ DQ4
R
DQ 13 DQ 15 VSS VDD DQ0 DQ2
PIN DESCRIPTION
PIN CLK CKE CS BA0, BA1 A0 ~ A10 Clock Clock Enable Chip Select Bank Address A ddress Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE DQM0~3 DQ0 ~ DQ31 V D D /V S S V D D Q /V S S Q NC
Rev. 0.4/Nov. 01
3
HY5V62CF
FUNCTIONAL BLOCK DIAGRAM 512Kbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic & Timer Refresh Counter
CLK
Row Active
512Kx32 Bank 3 Row Pre Decoder 512Kx32 Bank 2 X decoder 512Kx32 Bank 1 X decoder 512Kx32 Bank 0 X decoder DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate
CKE CS RAS CAS WE DQM0 DQM1 DQM2 DQM3
State Machine
Column Active
X decoder
Memory Cell Array
Column Pre Decoder Y decoder
DQ30 DQ31
Bank Select
Column Add Counter
A0 A1 Address buffers A10 BA0 BA1
Address Register Burst Counter
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.4/Nov. 01
4
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